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ADS5560IRGZT Datasheet(PDF) 4 Page - Texas Instruments |
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ADS5560IRGZT Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 53 page  ELECTRICAL CHARACTERISTICS ADS5560 ADS5562 SLWS207 – MAY 2008 ....................................................................................................................................................................................................... www.ti.com Typical values are at 25 °C, AVDD = DRVDD = 3.3 V, sampling rate = Max Rated, sine wave input clock, 1.5 V PP clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine gain (1dB). Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling rate = Max Rated, unless otherwise noted. ADS5562 ADS5560 TEST PARAMETER UNIT CONDITIONS MIN TYP MAX MIN TYP MAX RESOLUTION 16 16 bits ANALOG INPUT Differential input voltage VPP 3.56 3.56 range (1) Differential input 5 5 pF capacitance Analog input bandwidth 300 300 MHz Analog input common 6.6 6.6 µA/MSPS mode current (per input pin) VCM Common mode output Internal reference 1.5 1.5 V voltage mode VCM output current Internal reference ±4 ±4 mA capability mode DC ACCURACY No Missing Codes 0 dB gain Assured Assured DNL Differential non-linearity -0.95 0.5 3 -0.95 0.5 3 LSB INL Integral non-linearity -8.5 ±3 8.5 -8.5 ±3 8.5 LSB Offset error -25 ±10 25 -25 ±10 25 mV Offset error temperature 0.005 0.005 mV/ °C coefficient Variation of offset error 1.5 1.5 mV/V across AVDD supply There are two sources of gain error: i) internal reference inaccuracy and ii) channel gain error EGREF Gain error due to internal -2.5 ±1 2.5 -2.5 ±1 2.5 %FS reference inaccuracy alone ECHAN Channel gain error alone -2.5 ± 1 2.5 -2.5 ± 1 2.5 %FS Channel gain error 0.01 0.01 Δ%/ °C temperature coefficient POWER SUPPLY IAVDD Analog supply current 210 250 160 190 mA LVDS mode 52 44 mA IO = 3.5 mA, RL = Digital supply current 100 Ω IDRVDD CL = 5 pF CMOS mode 60 37 mA FIN = 3 MHz Total power LVDS mode 865 1100 674 810 mW Standby power STANDBY mode 155 135 mW with clock running Clock stop power 125 150 125 150 mW (1) The full-scale voltage range is a function of the fine gain settings. See Table 23. 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS5560 ADS5562 |
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