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TMS320C6414T Datasheet(PDF) 83 Page - Texas Instruments |
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TMS320C6414T Datasheet(HTML) 83 Page - Texas Instruments |
83 / 142 page TMS320C6414T, TMS320C6415T, TMS320C6416T FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS226L − NOVEMBER 2003 − REVISED FEBRUARY 2008 83 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 INPUT AND OUTPUT CLOCKS (CONTINUED) timing requirements for ECLKIN for EMIFA and EMIFB†‡§¶ (see Figure 19) NO. −600 −720 −850 −1G UNIT MIN MAX 1 tc(EKI) Cycle time, ECLKIN CVDD = 1.2 V 6# 16P ns 1 tc(EKI) Cycle time, ECLKIN CVDD = 1.1 V 7.5# 16P ns 2 tw(EKIH) Pulse duration, ECLKIN high 2.7 ns 3 tw(EKIL) Pulse duration, ECLKIN low 2.7 ns 4 tt(EKI) Transition time, ECLKIN 2 ns 5 tJ(EKI) Period jitter, ECLKIN 0.02E ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. § These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted. ¶ E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. # Minimum ECLKIN cycle times must be met, even when ECLKIN is generated by an internal clock source. Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. ECLKIN 2 3 4 4 5 1 Figure 19. ECLKIN Timing for EMIFA and EMIFB switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and EMIFB modules§¶||k (see Figure 20) NO. PARAMETER −600 −720 −850 −1G UNIT MIN MAX 1 tJ(EKO1) Period jitter, ECLKOUT1 0 ±175h ps 2 tw(EKO1H) Pulse duration, ECLKOUT1 high EH − 0.7 EH + 0.7 ns 3 tw(EKO1L) Pulse duration, ECLKOUT1 low EL − 0.7 EL + 0.7 ns 4 tt(EKO1) Transition time, ECLKOUT1 1 ns 5 td(EKIH-EKO1H) Delay time, ECLKIN high to ECLKOUT1 high 0.8 8 ns 6 td(EKIL-EKO1L) Delay time, ECLKIN low to ECLKOUT1 low 0.8 8 ns § These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted. ¶ E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. || The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. kEH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA or EMIFB. hThis cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock. |
Similar Part No. - TMS320C6414T_08 |
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Similar Description - TMS320C6414T_08 |
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