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SLRC400 Datasheet(PDF) 10 Page - NXP Semiconductors |
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SLRC400 Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 130 page  Philips Semiconductors Product Specification Rev. 2.0 November 2001 I •CODE Reader IC SL RC400 10 Preliminary 3.2 Pin Description Pin Types: I...Input; O...Output; PWR...Power PIN SYMBOL TYPE DESCRIPTION 1 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 13.56 MHz). 2 IRQ O Interrupt Request: output to signal an interrupt event 3 RFU I This Pin should be connected to Ground 4 SIGOUT O I •CODE Interface Output: delivers a serial data stream according to I•CODE1 and ISO 15693 5 TX1 O Transmitter 1: delivers the modulated 13.56 MHz carrier frequenzy 6 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 7 TX2 O Transmitter 2: delivers the modulated 13.56 MHz carrier frequenzy 8 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 9 NCS I Not Chip Select: selects and activates the µ-Processor interface of the SL RC400 NWR I Not Write: strobe to write data (applied on D0 to D7) into the SL RC400 register R/NW I Read Not Write: selects if a read or write cycle shall be performed. 10 1 nWrite I Not Write: selects if a read or write cycle shall be performed NRD I Not Read: strobe to read data from the SL RC400 register (applied on D0 to D7) NDS I Not Data Strobe: strobe for the read and the write cycle 11 1 nDStrb I Not Data Strobe: strobe for the read and the write cycle 12 DVSS PWR Digital Ground D0 to D7 I/O 8 Bit Bi-directional Data Bus 13 … 20 1 AD0 to AD7 I/O 8 Bit Bi-directional Address and Data Bus ALE I Address Latch Enable: strobe signal to latch AD0 to AD5 into the internal address latch when HIGH. AS I Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch when HIGH. 21 1 nAStrb I Not Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch when LOW. A0 I Address Line 1: Bit 0 of register address 22 1 nWait O Not Wait: signals with LOW that an access-cycle may started and with HIGH that it may be finished. 23 A1 I Address Line 1: Bit 1 of register address 24 A2 I Address Line 2: Bit 2 of register address 25 DVDD PWR Digital Power Supply 26 AVDD PWR Analog Power Supply 1 These pins offer different functionality according to the selected µ-Processor interface type. For detailed information refer to chapter 4. |
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Similar Description - SLRC400 |
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