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M74HC40102F1R Datasheet(PDF) 9 Page - STMicroelectronics |
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M74HC40102F1R Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 14 page EXAMPLE OF TYPICAL APPLICATION PROGRAMMABLE DIVIDE-BY-N COUNTER • fOUT = fIN N + 1 •Timing chart when N = ”3” (J0, J1 = VCC, J2 – J7 = GND) • HC40102... 1/2 to 1/100 are dividable • HC40103... 1/2 to 1/256 are dividable PARALLEL CARRY CASCADING * At synchronous cascade connection, huzzerd occurs at C0 output after its second stage when digitplace changes, due to delay arrival. Therefore, take gate from HC32 or the like, not from C0 output at the rear stage directly. PROGRAMMABLE TIMER Note :The above formula does not take into account the phase of clock input. Therefore, the real pulse width is the distance between the above formula-1/fIN ∼ the above formula. M54/M74HC40102/40103 9/14 |
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