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MCF52210CAE66 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MCF52210CAE66 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 56 page  MCF52211 Family Configurations MCF52211 ColdFire Microcontroller, Rev. 1 Freescale Semiconductor 3 1 MCF52211 Family Configurations Figure 1 shows a top-level block diagram of the MCF52211. Package options for this family are described later in this document. Table 1. MCF52211 Family Configurations Module 52210 52211 52212 52213 Version 2 ColdFire Core with MAC (Multiply-Accumulate Unit) •••• System Clock 66, 80 MHz 50 MHz Performance (Dhrystone 2.1 MIPS) up to 76 up to 46 Flash / Static RAM (SRAM) 64/16 Kbytes 128/16 Kbytes 64/8 Kbytes 128/8 Kbytes Interrupt Controller (INTC) •••• Fast Analog-to-Digital Converter (ADC) •••• USB On-The-Go (USB OTG) •••• Four-channel Direct-Memory Access (DMA) •••• Software Watchdog Timer (WDT) •••• Secondary Watchdog Timer •••• Two-channel Periodic Interrupt Timer (PIT) 2 2 2 2 Four-Channel General Purpose Timer (GPT) •••• 32-bit DMA Timers 4 4 4 4 QSPI •••• UART(s) 2 3 2 2 I2C2 2 2 2 Eight/Four-channel 8/16-bit PWM Timer •••• General Purpose I/O Module (GPIO) •••• Chip Configuration and Reset Controller Module •••• Background Debug Mode (BDM) •••• JTAG - IEEE 1149.1 Test Access Port1 1 The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on smaller packages. •••• Package 64 LQFP/QFN 81 MAPBGA 64 LQFP/QFN 81 MAPBGA 100 LQFP 64 LQFP 64 LQFP |
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Similar Description - MCF52210CAE66 |
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