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TLV320AIC28IRGZ Datasheet(PDF) 11 Page - Texas Instruments |
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TLV320AIC28IRGZ Datasheet(HTML) 11 Page - Texas Instruments |
11 / 85 page TLV320AIC28 SLAS418B − FEBRUARY 2004 − REVISED MAY 2005 www.ti.com 11 AUDIO INTERFACE TIMING DIAGRAMS ts(DI) th(DI) td(DO−BCLK) td(DO−WS) WCLK BCLK SDOUT SDIN td(WS) Figure 1. DSP Timing in Master Mode Typical Timing Requirements (see Figure 1) PARAMETER(1) IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER(1) MIN MAX MIN MAX UNITS td(WS) WCLK delay 30 15 ns td(DO−WS) WCLK to DOUT delay (for LJF mode) 30 15 ns td(DO−BCLK) BCLK to DOUT delay 30 15 ns ts(DI) SDIN setup 6 6 ns th(DI) SDIN hold 6 6 ns tr Rise time 18 6 ns tf Fall time 18 6 ns (1) These parameters are based on characterization and are not tested in production. ts(DI) th(DI) td(DO−BCLK) WCLK BCLK SDOUT SDIN td(WS) td(WS) Figure 2. DSP Timing in Master Mode Typical Timing Requirements (see Figure 2) PARAMETER(1) IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER(1) MIN MAX MIN MAX UNITS td(WS) WCLK delay 30 15 ns td(DO−BCLK) BCLK to DOUT delay 30 15 ns ts(DI) SDIN setup 6 6 ns th(DI) SDIN hold 6 6 ns tr Rise time 18 6 ns tf Fall time 18 6 ns (1) These parameters are based on characterization and are not tested in production. |
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