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TPS79928DDCRG4 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS79928DDCRG4 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 21 page www.ti.com Output Noise V N + 10.7mV RMS V V OUT (1) Board Layout Recommendations to Improve PSRR and Noise Performance Internal Current Limit Shutdown Dropout Voltage Startup TPS799xx SBVS056E – JANUARY 2005 – REVISED OCTOBER 2005 In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the TPS799xx, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01µF noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce noise. A parallel combination that gives 2µA of divider current will have the same noise performance as a fixed voltage version. To further optimize noise, equivalent series resistance of the output capacitor can be set to approximately 0.2 Ω. This configuration maximizes phase margin in the control loop, reducing total output noise by up to 10%. Noise can be referred to the feedback point (FB pin) such that with CNR = 0.01µF total noise is approximately given by Equation 1: The TPS79901 adjustable version does not have the noise-reduction pin available, so ultra-low noise operation is not possible. Noise can be minimized according to the above recommendations. To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. The TPS799xx internal current limit helps protect the regulator during fault conditions. During current limit, the output will source a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in current limit for extended periods of time. The PMOS pass element in the TPS799xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate. The enable pin (EN) is active high and is compatible with standard and low voltage TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN. The TPS799xx uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS,ON of the PMOS pass element. Because the PMOS device behaves like a resistor in dropout, VDO will approximately scale with output current. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 18 through Figure 20 in the Typical Characteristics section. Fixed voltage versions of the TPS799xx use a quick-start circuit to fast-charge the noise reduction capacitor, CNR, if present (see Functional Block Diagrams, Figure 1). This allows the combination of very low output noise and fast start-up times. The NR pin is high impedance so a low leakage CNR capacitor must be used; most ceramic capacitors are appropriate in this configuration. Note that for fastest startup, VIN should be applied first, then the enable pin (EN) driven high. If EN is tied to IN, startup will be somewhat slower. Refer to Figure 25 and Figure 26 in the Typical Characteristics section. The quick-start switch is closed for approximately 135µs. To ensure that CNR is fully charged during the quick-start time, a 0.01µF or smaller capacitor should be used. 11 |
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