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M58MR032C120ZC6T Datasheet(PDF) 9 Page - STMicroelectronics |
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M58MR032C120ZC6T Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 52 page  9/52 M58MR032C, M58MR032D Figure 4. Single Synchronous Read Sequence (RSIG, RCFI, RSR instructions) AI90022 A20-A16 VALID ADDRESS L ADQ15-ADQ0 VALID ADDRESS VALID DATA NOT VALID ADQ15-ADQ0 VALID ADDRESS VALID DATA ADQ15-ADQ0 VALID ADDRESS NOT VALID NOT VALID NOT VALID CONFIGURATION CODE 4 CONFIGURATION CODE 3 CONF. CODE 2 NOT VALID NOT VALID VALID DATA K Both Chip Enable E and Output Enable G must be at VIL in order to read the output of the memory. Read array is the default state of the device when exiting power down or after power up. Burst Read. The device also supports a burst read. In this mode a burst sequence is started at the first clock edge (rising or falling according to configuration settings) after the falling edge of L. After a configurable delay of 2 to 5 clock cycles a new data is output at each clock cycle. The burst sequence may be configured for linear or inter- leaved order and for a length of 4, 8 words or for continuous burst mode. Wrap and no-wrap modes are also supported. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst se- quence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. See the Write Read Configuration Reg- ister (CR) Instruction for more details on all the possible settings for the synchronous burst read (see Table 14). It is possible to perform burst read across bank boundary (all banks in read array mode). Write. Write operations are used to give Instruc- tion Commands to the memory or to latch Input Data to be programmed. A write operation is initi- ated when Chip Enable E and Write Enable W are at VIL with Output Enable G at VIH. Addresses are latched on the rising edge of L. Commands and In- put Data are latched on the rising edge of W or E whichever occurs first. Noise pulses of less than 5ns typical on E, W and G signals do not start a write cycle. Write operations are asynchronous and clock is ignored during write. Dual Bank Operations. The Dual Bank allows to run different operations simultaneously in the two banks. It is possible to read array data from one bank while the other is programming, erasing or reading any data (CFI, status register or electronic signature). Read and write cycles can be initiated for simulta- neous operations in different banks without any delay. Only one bank at a time is allowed to be in program or erase mode, while the other must be in one of the read modes (see Table 8). Commands must be written to an address within the block targeted by that command. Output Disable. The data outputs are high im- pedance when the Output Enable G is at VIH with Write Enable W at VIH. Standby. The memory is in standby when Chip Enable E is at VIH and the P/E.C. is idle. The pow- er consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Standby. When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically en- ters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while out- puts still drive the bus. The automatic standby fea- ture is not available when the device is configured for synchronous burst mode. |
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