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SN75HVD1176 Datasheet(PDF) 5 Page - Texas Instruments |
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SN75HVD1176 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 19 page www.ti.com THERMAL CHARACTERISTICS (1) PARAMETER MEASUREMENT INFORMATION II IO IO VOD 50pF 27 Ω 27 Ω VOC 0Vor3V A B D SN65HVD1176 SN75HVD1176 SLLS563D – JULY 2003 – REVISED DECEMBER 2007 Table 1. SUPPLY CURRENT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Driver and receiver, RE at 0 V, DE at VCC, All other inputs open, no load 4 6 mA Driver only, RE at VCC, DE at VCC, All other inputs open, no load 3.8 6 mA Supply ICC Current(1) Receiver only, RE at 0 V, DE at 0 V, All other inputs open, no load 3.6 6 mA Standby only, RE at VCC, DE at 0 V, All other inputs open 0.2 5 µA (1) Over recommended operating conditions over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT Low-K board(4), no air flow 208.3 °C/W θ JA Junction-to-ambient thermal resistance(3) High-K board(5), no air flow 128.7 °C/W θ JB Junction-to-board thermal resistance High-K board 77.6 °C/W θ JC Junction-to-case thermal resistance 43.9 °C/W RL = 54 Ω, CL = 50 pF, 0 V to 3 V, PD Device power dissipation 15 MHz, 50% duty cycle square wave 277 318 mW input, driver and receiver enabled SN65HVD1176 –40 64 °C Low-K board, no air flow, PD = 318 mW SN75HVD1176 0 °C TA Ambient air temperature SN65HVD1176 –40 89 °C High-K board, no air flow, PD = 318 mW SN75HVD1176 0 °C TSD Thermal shut down junction temperature 150 °C (1) See Application Information section for an explanation of these parameters. (2) All typical values are with VCC = 5 V and TA = 25°C. (3) The intent of θ JA specification is solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. (4) JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. (5) JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. NOTE: Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle, Zo = 50 Ω (unless otherwise specified). Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading Copyright © 2003–2007, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): SN65HVD1176 SN75HVD1176 |
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