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TMS320DM642AGNZA5 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM642AGNZA5 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 176 page  www.ti.com 1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor 1.1 Features TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200L – JULY 2002 – REVISED JANUARY 2007 – 1024M-Byte Total Addressable External • High-Performance Digital Media Processor Memory Space – 2-, 1.67-, 1.39-ns Instruction Cycle Time • Enhanced Direct-Memory-Access (EDMA) – 500-, 600-, 720-MHz Clock Rate Controller (64 Independent Channels) – Eight 32-Bit Instructions/Cycle – 4000, 4800, 5760 MIPS • 10/100 Mb/s Ethernet MAC (EMAC) – Fully Software-Compatible With C64x™ – IEEE 802.3 Compliant – Media Independent Interface (MII) • VelociTI.2™ Extensions to VelociTI™ – 8 Independent Transmit (TX) Channels and Advanced Very-Long-Instruction-Word (VLIW) 1 Receive (RX) Channel TMS320C64x™ DSP Core – Eight Highly Independent Functional Units • Management Data Input/Output (MDIO) With VelociTI.2™ Extensions: • Three Configurable Video Ports • Six ALUs (32-/40-Bit), Each Supports – Providing a Glueless I/F to Common Video Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Decoder and Encoder Devices Arithmetic per Clock Cycle – Supports Multiple Resolutions/Video Stds • Two Multipliers Support Four 16 x 16-Bit • VCXO Interpolated Control Port (VIC) Multiplies (32-Bit Results) per Clock – Supports Audio/Video Synchronization Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle • Host-Port Interface (HPI) [32-/16-Bit] – Load-Store Architecture With Non-Aligned • 32-Bit/66-MHz, 3.3-V Peripheral Component Support Interconnect (PCI) Master/Slave Interface – 64 32-Bit General-Purpose Registers Conforms to PCI Specification 2.2 – Instruction Packing Reduces Code Size • Multichannel Audio Serial Port (McASP) – All Instructions Conditional – Eight Serial Data Pins • Instruction Set Features – Wide Variety of I2S and Similar Bit Stream – Byte-Addressable (8-/16-/32-/64-Bit Data) Format – 8-Bit Overflow Protection – Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, – Bit-Field Extract, Set, Clear CP-430 Formats – Normalization, Saturation, Bit-Counting • Inter-Integrated Circuit (I2C Bus™) – VelociTI.2™ Increased Orthogonality • Two Multichannel Buffered Serial Ports • L1/L2 Memory Architecture – 128K-Bit (16K-Byte) L1P Program Cache • Three 32-Bit General-Purpose Timers (Direct Mapped) • Sixteen General-Purpose I/O (GPIO) Pins – 128K-Bit (16K-Byte) L1D Data Cache (2-Way • Flexible PLL Clock Generator Set-Associative) • IEEE-1149.1 (JTAG) Boundary- – 2M-Bit (256K-Byte) L2 Unified Mapped Scan-Compatible RAM/Cache (Flexible RAM/Cache Allocation) • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch • Endianess: Little Endian, Big Endian • 548-Pin Ball Grid Array (BGA) Package • 64-Bit External Memory Interface (EMIF) (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch – Glueless Interface to Asynchronous Memories (SRAM and EPROM) and • 0.13-µm/6-Level Cu Metal Process (CMOS) Synchronous Memories (SDRAM, SBSRAM, • 3.3-V I/O, 1.2-V Internal (-500) ZBT SRAM, and FIFO) • 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600, -720) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. Windows is a registered trademark of Microsoft Corporation. I2C Bus is a trademark of Philips Electronics N.V.. PRODUCTION DATA information is current as of publication date. Copyright © 2002–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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