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M68AW127BM70NK1T Datasheet(PDF) 11 Page - STMicroelectronics

Part # M68AW127BM70NK1T
Description  1Mbit 128K x8, 3.0V Asynchronous SRAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M68AW127BM70NK1T Datasheet(HTML) 11 Page - STMicroelectronics

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M68AW127B
Write Mode
The M68AW127B is in the Write mode whenever
the W and E1 pins are Low and the E2 pin is High.
Either the Chip Enable input (E1) or the Write En-
able input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
Write begins with the concurrence of E1 being ac-
tive with W low. Therefore, address setup time is
referenced to Write Enable and Chip Enable as
tAVWL and tAVEH, respectively, and is determined
by the latter occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E1, or W.
If the Output is enabled (E1 = Low, E2 = High and
G = Low), then W will return the outputs to high im-
pedance within tWLQZ of its falling edge. Care must
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for tDVWH before
the rising edge of Write Enable, or for tDVEH before
the rising edge of E1, whichever occurs first, and
remain valid for tWHDX or tEHDX.
Figure 11. Write Enable Controlled, Write AC Waveforms
AI05478
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A16
E1
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
E2
tELWH


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