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TMS320DM6467 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM6467 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 340 page  1 Digital Media System-on-Chip (DMSoC) 1.1 Features TMS320DM6467 Digital Media System-on-Chip www.ti.com SPRS403A – DECEMBER 2007 – REVISED MAY 2008 • High-Performance Digital Media SoC • ARM926EJ-S Core – 594-MHz C64x+™ Clock Rate – Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets – 297-MHz ARM926EJ-S™ Clock Rate – DSP Instruction Extensions and Single – Eight 32-Bit C64x+ Instructions/Cycle Cycle MAC – 4752 C64x+ MIPS – ARM® Jazelle® Technology – Fully Software-Compatible With C64x / – EmbeddedICE-RT™ Logic for Real-Time ARM9™ Debug • Advanced Very-Long-Instruction-Word (VLIW) • ARM9 Memory Architecture TMS320C64x+™ DSP Core – 16K-Byte Instruction Cache – Eight Highly Independent Functional Units – 8K-Byte Data Cache • Six ALUs (32-/40-Bit), Each Supports – 32K-Byte RAM Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle – 8K-Byte ROM • Two Multipliers Support Four 16 x 16-Bit • Embedded Trace Buffer™ (ETB11™) With 4KB Multiplies (32-Bit Results) per Clock Memory for ARM9 Debug Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • Endianness: Little Endian for ARM and DSP Results) per Clock Cycle • Dual Programmable High-Definition Video – Load-Store Architecture With Non-Aligned Image Co-Processor (HDVICP) Engines Support – Supports a Range of Encode, Decode, and – 64 32-Bit General-Purpose Registers Transcode Operations – Instruction Packing Reduces Code Size • H.264, MPEG2, VC1, MPEG4 SP/ASP – All Instructions Conditional • Video Port Interface (VPIF) – Additional C64x+™ Enhancements – Two 8-Bit SD (BT.656), Single 16-Bit HD • Protected Mode Operation (BT.1120), or Single Raw (8-/10-/12-Bit) • Exceptions Support for Error Detection Video Capture Channels and Program Redirection – Two 8-Bit SD (BT.656) or Single 16-Bit HD • Hardware Support for Modulo Loop (BT.1120) Video Display Channels Operation • Video Data Conversion Engine (VDCE) • C64x+ Instruction Set Features – Horizontal and Vertical Downscaling – Byte-Addressable (8-/16-/32-/64-Bit Data) – Chroma Conversion (4:2:2 ↔4:2:0) – 8-Bit Overflow Protection • Two Transport Stream Interface (TSIF) – Bit-Field Extract, Set, Clear Modules – Normalization, Saturation, Bit-Counting (One Parallel/Serial and One Serial Only) – Compact 16-Bit Instructions – TSIF for MPEG Transport Stream – Additional Instructions to Support Complex – Simultaneous Synchronous or Multiplies Asynchronous Input/Output Streams • C64x+ L1/L2 Memory Architecture – Absolute Time Stamp Detection – 32K-Byte L1P Program RAM/Cache (Direct – PID Filter With 7 PID Filter Tables Mapped) – Corresponding Clock Reference Generator – 32K-Byte L1D Data RAM/Cache (2-Way (CRGEN) Modules for System Time-Clock Set-Associative) Recovery – 128K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2007–2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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