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TMS320DM6443AZWT Datasheet(PDF) 7 Page - Texas Instruments |
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TMS320DM6443AZWT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 223 page  Revision History TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282F – DECEMBER 2005 – REVISED MARCH 2008 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the SPRS282E device-specific data manual to make it an SPRS282F revision. Scope: Applicable updates to the DM64x device family, specifically relating to the TMS320DM6443 device, have been incorporated. • Updated the C64x+ Megamodule Revision, JTAG BSDL_ID, and JTAG ID Register to include Silicon Revision 2.1 TMS320DM6443 Revision History SEE ADDITIONS/MODIFICATIONS/DELETIONS Global • Updated/changed all HCS instances from "HCS" to "HCS"; HCS is an active low signal Section 2.4.2 Section 2.4.2.4, C64x+ CPU: DSP Memory Mapping • Updated/changed "... The Level 1 program cache (L1D) ..." to "... The Level 1 program cache (L1P) ..." [Cleared Documentation Feedback Issue] Section 3.5.2 Table 3-13, DM6443 Multiplexed Peripheral Pins and Multiplexing Controls: Multiplexed Pin • Deleted the "VPFE CCD, GPIO" row; N/A to this device Configurations Section 2.7 Table 2-23, ATA/CF Terminal Functions: Terminal Functions • Updated/changed the table to include the HPI pin muxing functions Section 2.8.2 Figure 2-6, Device Nomenclature: Device and • Updated/changed the figure to include Silicon Revision 2.1 Development-Support Tool Nomenclature Section 3.2.1 Table 3-2, CHP_SHRTSW Register Description: Power Configurations • Updated/changed the DSPPWRON bit description for "0" and "1" at Reset Section 3.5.6.4 Table 3-21, ATA, EMIFA, and GPIO Pin Multiplexing Control: ATA, EMIFA, UART1, • Updated/changed the "RDY/BSY/EM_WAIT" column head to "EM_WAIT/IORDY" and corrected the SPI, and GPIO Pin column data [Cleared Documentation Feedback Issue] Multiplexing • Added associated footnote Section 3.5.6.10 Table 3-32, HPI and EMIFA/ATA Pin Multiplexing: HPI and EMIFA/ATA • Updated/changed the "HRDY/RDY/BSY/EM_WAIT" column head to "HRDY/EM_WAIT/IORDY" and Pin Multiplexing corrected the column data [Cleared Documentation Feedback Issue] Section 6.10.1.2 Table 6-35, Switching Characteristics Over Recommended Operating Conditions for Asynchronous EMIFA Eelctrical Memory Cycles for EMIFA Module: Data/Timing Updated/changed the following parameter information: • Parameter NO. 4 tsu(EMCSL-EMOEL), Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0) MAX value from "(RS + 1) * E + 1.2" to "(RS + 1) * E + 1.4" ns • Parameter NO. 5 th(EMOEH-EMCSH), Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0) MIN value from "(RH + 1) * E - 1.3" to "(RH + 1) * E - 2.1" ns • Parameter NO. 5 th(EMOEH-EMCSH), Output hold time, EM_OE high to EM_CS[5:2] high (SS = 1) MIN value from "-1.4" to "-2.2" ns • Parameter NO. 7 th(EMOEH-EMBAIV), Output hold time, EM_OE high to EM_BA[1:0] invalid MIN value from "(RH + 1) * E - 2.1" to "(RH + 1) * E - 2.3" ns • Parameter NO. 9 th(EMOEH-EMAIV), Output hold time, EM_OE high to EM_A[21:0] invalid MIN value from "(RH + 1) * E - 2.4" to "(RH + 1) * E - 2.6" ns • Parameter NO. 17 th(EMWEH-EMCSH), Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0) MIN value from "(WH + 1) * E - 1.4" to "(WH + 1) * E - 2.1" ns • Parameter NO. 17 th(EMWEH-EMCSH), Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1) MIN value from "-1.4" to "-2.1" ns • Parameter NO. 21 th(EMWEH-EMBAIV), Output hold time, EM_WE high to EM_BA[1:0] invalid MIN value from "(WH + 1) * E - 2.2" to "(WH + 1) * E - 2.3" ns • Parameter NO. 23 th(EMWEH-EMAIV), Output hold time, EM_WE high to EM_A[21:0] invalid MIN value from "(WH + 1) * E - 2.5" to "(WH + 1) * E - 2.6" ns Submit Documentation Feedback Revision History 7 |
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