 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SN74ABTH18502APMR Datasheet(PDF) 6 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
SN74ABTH18502APMR Datasheet(HTML) 6 Page - Texas Instruments |
|
|
6 / 42 page  SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 test architecture Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram. The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully one-half of the TCK cycle. The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the TAP controller, and the test registers. As illustrated, the device contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register. Test-Logic-Reset Run-Test/Idle Select-DR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Update-DR TMS = L TMS = L TMS = H TMS = L TMS = H TMS = H TMS = L TMS = H TMS = L TMS = L TMS = H TMS = L Exit2-DR Select-IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Update-IR TMS = L TMS = L TMS = H TMS = L TMS = H TMS = H TMS = L TMS = H TMS = L Exit2-IR TMS = L TMS = H TMS = H TMS = H TMS = L TMS = H TMS = L TMS = H TMS = H TMS = H TMS = L Figure 1. TAP-Controller State Diagram |
Similar Part No. - SN74ABTH18502APMR |
|
Similar Description - SN74ABTH18502APMR |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
