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RIVA128ZX Datasheet(PDF) 69 Page - STMicroelectronics |
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RIVA128ZX Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 85 page  128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX 69/85 APPENDIX Descriptions of register contents include an indication if register fields are readable (R) or writable (W) and the initial power-on or reset value of the field (I). ‘-’ indicates not readable / writable, X indicates an inde- terminate value, hence I=X indicates register or field not reset. A PCI CONFIGURATION REGISTERS This section describes the 256 byte PCI configuration spaces as implemented by the RIVA128ZX. A single PCI VGA device is defined by the RIVA128ZX which decodes and acknowledges the first 256 bytes of the configuration address space. The RIVA128ZX does not respond (does not assert DEVSEL#) for functions 1-7. A.1 REGISTER DESCRIPTIONS FOR PCI CONFIGURATION SPACE Byte offsets 0x03 - 0x00 Device Identification Register (0x03 - 0x02) Vendor Identification Register (0x01 - 0x00) 0x03 0x02 0x01 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 76543 210 Bits Function RW I 31:16 The DEVICE_ID_CHIP bits contain the chip number allocated by the manu- facturer to identify the particular device. = 0x0018 if the power-on reset configuration APCI Supported bit = 0 = 0x0019 if the power-on reset configuration APCI Supported bit = 1 R- X Bits Function RW I 15:0 VENDOR_ID bits allocated by the PCI Special Interest Group to uniquely identify the manufacturer of the device. NVIDIA/STMicroelectronics Vendor ID = 0x12D2 (4818) R- X |
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