TLV320AIC26IRHBG4 datasheet(8/67 Pages) TI

Part #	TLV320AIC26IRHBG4

Description	LOW POWER STEREP AUDIO CODEC WITH HEADPHONE / SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC

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TLV320AIC26

SLAS412− DECEMBER 2003

www.ti.com

8

SPI TIMING DIAGRAM

t

td

t

a

t

sck

t Lead

t Lag

t wsck

t r

t f

t v

t ho

t dis

t hi

t su

SS

SCLK

MISO

MOSI

MSB OUT

BIT . . . 1

LSB OUT

MSB OUT

BIT . . . 1

LSB OUT

TYPICAL TIMING REQUIREMENTS

All specifications at 25

°C, DVDD = 1.8 V (1)

PARAMETER

IOVDD = 1.1 V

IOVDD = 3.3 V

UNITS

PARAMETER

MIN

MAX

MIN

MAX

UNITS

twsck

SCLK pulse width

27

18

ns

tLead

Enable lead time

18

15

ns

tLag

Enable lag time

18

15

ns

ttd

Sequential transfer delay

18

15

ns

ta

Slave MISO access time

18

15

ns

tdis

Slave MISO disable time

18

15

ns

tsu

MOSI data setup time

6

ns

thi

MOSI data hold time

6

ns

tho

MISO data hold time

4

ns

tv

MISO data valid time

22

13

ns

tr

Rise time

6

4

ns

tf

Fall time

6

4

ns

(1) These parameters are based on characterization and are not tested in production.

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TLV320AIC26IRHBG4 Datasheet(PDF) 8 Page - Texas Instruments

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