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2

IRS2133/IRS2135 (J&S)PbF

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are

Recommended Operating Conditions

The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the

tested with all supplies biased at a 15 V differential.

Note 1:

Note 2:

The CAO pin and all input pins (except CA+ & CA-) are internally clamped with a 5.2 V zener diode.

Symbol

Definition

Min.

Max.

Units

High side floating supply voltage

-0.3

625

High side floating offset voltage

High side floating output voltage

Fixed supply voltage

-0.3

25

Logic ground

Low side output voltage

-0.3

Logic input voltage ( HIN, LIN ITRIP, SD & FLT-CLR)

Operational amplifier input voltage (CA+ & CA-)

Operational amplifier output voltage (CAO)

FAULT output voltage

V

Allowable offset supply voltage transient

—

50

V/ns

(28 lead PDIP)

—

1.5

(28 lead SOIC)

—

1.6

(44 lead PLCC)

—

2.0

W

(28 lead PDIP)

—

83

(28 lead SOIC)

—

78

Thermal resistance, junction to ambient

(44 lead PLCC)

—

63

°C/W

Junction temperature

—

150

Storage temperature

-55

150

Lead temperature (soldering, 10 seconds)

—

300

°C

Symbol

Definition

Min.

Max.

Units

High side floating supply voltage

High side floating offset voltage

Note 1

600

High side floating output voltage

Fixed supply voltage

10 or 12

20

Low side driver return

-5

5

Low side output voltage

0

Logic input voltage (HIN, LIN ITRIP, SD & FLT-CLR)

Operational amplifier input voltage (CA+ & CA-)

Operational amplifier output voltage (CAO)

FAULT output voltage

V

PRELIMINARY