CS5543-KL datasheet(4/30 Pages) CIRRUS

Part #	CS5543-KL

Description	22-Bit, Multi-Channel DS ADC Chip Set

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Manufacturer	CIRRUS [Cirrus Logic]

Direct Link	http://www.cirrus.com

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CS5542 CS5543

4

DS109PP2

CS5542 / CS5543 SYSTEM SWITCHING CHARACTERISTICS: (T

A= 25°C, VD1+ =

VD2+ = VD3+ = 5 V

±5%; GND1 = GND2 = GND3 = 0 V; For timing parameters: CLKIN= 2.048 MHz; DATACLK =

6.144 MHz; MCLK = 2.048 MHz; Outputs loaded with 50 pF.)

Parameter

Number

Min

Typ

Max

Units

CS5542 Modulator Timing

MCLK Frequency

0

1.024

-

2.048

MHz

MCLK Duty Cycle

1

40

-

60

%

FSYNC Frequency

2

-

MCLK/

16

-Hz

FSYNC set-up before MCLK rising edge

3

70

-

ns

FSYNC hold time after MCLK rising edge

4

70

-

ns

MCLK rising to MDATA[3:0] valid

5

70

ns

MCLK rising to MDATA[3:0] high

6

70

ns

MCLK falling to MDATA[3:0] to Hi-Z

7

70

ns

MCLK falling to MDATA[3:0] active

8

70

ns

CS5543 System Timing

CLKIN Frequency

(1/Clock Period)

9

1.024

-

2.048

MHz

CLKIN Duty Cycle

10

40

-

60

%

DATACLK Frequency

(1/Clock Period)

11

3.072

-

6.144

MHz

DATACLK Duty Cycle

12

40

-

60

%

FRAME rising to CLKIN rising

13

20

ns

FRAME rising to next DATACLK rising

14

20

ns

FRAME period

15

1

ms

CLKIN rising to MCLK rising

16

0

50

ns

CLKIN falling to MCLK falling

17

0

50

ns

CS5542 /CS5543 Interface

FSYNC period

18

-

7.81

-

µs

MCLK falling to FSYNC rising or falling

19

0

70

ns

CS5543 to CS5543 Interface

DATACLK rising to DATAOUT valid

20

65

ns

DATAIN set-up time before DATACLK rising

21

0

15

ns

DATAIN hold time after DATACLK rising

22

15

ns

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CS5543-KL Datasheet(PDF) 4 Page - Cirrus Logic

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