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SN65LVCP40

SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006

Table 1. Signal Descriptions

SIGNAL

PIN(S)

TYPE

SIGNAL TYPE

DESCRIPTION

LINE SIDE HIGH-SPEED I/O

LI_0P

6

I (w/ 50-

Ω termination PECL/CML

Differential input, port_0 line side

LI_0N

7

to VBB)

compatible

LI_1P

30

I (w/ 50-

Ω termination PECL/CML

Differential input, port_1 line side

LI_1N

31

to VBB)

compatible

LO_0P

33

O

Differential output, port_0 line side

LO_0N

34

LO_1P

9

O

Differential output, port_1 line side

LO_1N

10

SWITCH SIDE HIGH-SPEED I/O

SIA_0P

40

I (w/ 50-

Ω termination CML/PECL

Differential input, mux_0 switch_A_side

SIA_0N

39

to VBB)

compatible

SIB_0P

43

I (w/ 50-

Ω termination CML/PECL

Differential input, mux_0 switch_B_side

SIB_0N

42

to VBB)

compatible

SIA_1P

16

I (w/ 50-

Ω termination CML/PECL

Differential input, mux_1 switch_A_side

SIA_1N

15

to VBB)

compatible

SIB_1P

19

I (w/ 50-

Ω termination CML/PECL

Differential input, mux_1 switch_B_side

SIB_1N

18

to VBB)

compatible

SOA_0P

46

O

Differential output, mux_0 switch_A_side

SOA_0N

45

SOB_0P

4

O

Differential output, mux_0 switch_B_side

SOB_0N

3

SOA_1P

22

O

Differential output, mux_1 switch_A_side

SOA_1N

21

SOB_1P

28

O

Differential output, mux_1 switch_B_side

SOB_1N

27

CONTROL SIGNALS

Output preemphasis control, line side port_0 and port_1. Has internal

PREL_0

12

I (w/ 35-k

Ω pullup)

LVTTL

pull-up. See Preemphasis Controls PREL_0, PREL_1, PRES_0 and

PREL_1

1

PRES for function definition.

Output preemphasis control, switch side port_0 and port_1. See

PRES_0

36

I (w/ 35-k

Ω pullup)

LVTTL

Preemphasis Controls PREL_0, PREL_1, PRES_0 and PRES for

PRES_1

25

function definition.

LB0A

47

Loopback control for mux_0 switch side. See Loopback Controls LB0A,

I (w/ 35-k

Ω pullup)

LVTTL

LB0B

48

LB0B, LB1A and LB1B for function definition.n

LB1A

23

Loopback control for mux_1 switch side. See Loopback Controls LB0A,

I (w/ 35-k

Ω pullup)

LVTTL

LB1B

24

LB0B, LB1A and LB1B for function definition.n

MUX_S0

37

Port A and B multiplex control of mux_0 and mux_1. See Multiplex

I (w/ 35-k

Ω pullup)

LVTTL

MUX_S1

13

Controls MUX_S0 and MUX_S1 for function definition.

No connect. This pin is unused and can be left open or tied to GND with

REXT

26

N/A

any resistor.

POWER SUPPLY

2, 8, 14,

20, 29,

VCC

PWR

Power supply 3.3 V ±5%

35, 38,

44

5, 11, 17,

GND

PWR

Power supply return

32, 41

The ground center pad is the metal contact at the bottom of the 48-pin

GND

package. It must be connected to the GND plane. At least 4 vias are

PWR

Center Pad

recommended to minimize inductance and provide a solid ground. See

the package drawing for the via placement.

(1)

VML stands for Voltage Mode logic; VML provides a differential output impedance of 100-

Ω. VML offers the benefits of CML and

consumes less power.

6

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