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TPS51727RHAR Datasheet(PDF) 9 Page - Texas Instruments |
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TPS51727RHAR Datasheet(HTML) 9 Page - Texas Instruments |
9 / 42 page TPS51727 www.ti.com .............................................................................................................................................................. SLUS806A – APRIL 2008 – REVISED MAY 2008 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. OSRSEL 38 I Overshoot reduction (OSR) setting. The OSR threshold can be selected or OSR can be disabled. PAD - - Thermal pad; Connect directly to system GND plane with multiple vias. PCNT 13 I Phase control input. 0.5-V threshold logic. High is dual phase mode. PD1 12 I Test pin. Tie to GND. PD2 15 PGOOD 31 O Open-drain PWRGD output. PGND 25 - Synchronous N-channel MOSFET gate drive return. PMON 35 O Power monitor output. VPMON = VOUT × ΣVISENSE × K. See applications section for more detail. SLP 32 I Sleep mode control. 3.3-V I/O Level; disallows switching when entering sleep mode. THAL 11 O Thermal alarm; open drain output, Active low. 1-ms de-glitch filter. Thermal sensor input. An internal 60- µA current source flows into an NTC thermistor connected to GND. The THRM 10 I/O voltage threshold is 0.75-V. Also is a ‘Faults off’ input, (VTHRM = VV5FILT) for debug mode. On-time selection pin. The operating frequency can be set between 200-kHz and 500-kHz in 100-kHz steps. TONSEL 37 I Frequency can be changed during operation. Overcurrent protection (OCP) setting. The valley current limit at the CS inputs can be selected in a range TRIPSEL 36 I between approximately 10-mV to 20-mV. V5IN 26 I 5-V power input for drivers; bypass to PGND with ≥ 1 µF ceramic capacitor. 5-V power input for control circuitry. Has internal, 3- Ω resistor to 5VFILT. Bypass to GND with ≥ 1-µF V5FILT 40 I ceramic capacitor. VBST1 22 I Top N-channel MOSFET bootstrap voltage inputs. VBST2 29 Voltage sense line tied directly to VOUT. Tie to VOUT with a 100- Ω resistor to close feedback when voltage VFB 9 I sensing through a socket. VID0 20 VID1 19 VID2 18 I DAC programming bits most significant bit (MSB) to least significant bit (LSB). 0.5-V threshold logic. VID3 17 VID4 16 VREF 2 O 1.7-V, 250- µA voltage reference. Bypass to GND with a 0.22-µF ceramic capacitor. Copyright © 2008, Texas Instruments Incorporated 9 Product Folder Link(s): TPS51727 |
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