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V437216S04VCTG-10PC Datasheet(PDF) 5 Page - Mosel Vitelic, Corp |
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V437216S04VCTG-10PC Datasheet(HTML) 5 Page - Mosel Vitelic, Corp |
5 / 11 page MOSEL VITELIC V437216S04V(C)TG-10PC 5 V437216S04V(C)TG-10PC Rev. 1.1 June 2000 DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V 30 Minimum RAS Pulse Width tRAS 45 ns 2D 31 Module Bank Density (Per Bank) 64 MByte 10 32 SDRAM Input Setup Time 2 ns 20 33 SDRAM Input Hold Time 1 ns 10 34 SDRAM Data Input Setup Time 2 ns 20 35 SDRAM Data Input Hold Time 1 ns 10 36-61 Superset Information (May be used in Future) 00 62 SPD Revision Revision 1.2 12 63 Checksum for Bytes 0 - 62 FD 64-125 Manufacturers’s Information (Optional) (FFh if not used) XX 126 Max. Frequency Specification 100 MHz 64 127 100 MHz Support Details AF 128+ Unused Storage Location 00 Symbol Parameter Limit Values Unit Min. Max. VIH Input High Voltage 2.0 VCC+0.3 V VIL Input Low Voltage –0.5 0.8 V VOH Output High Voltage (IOUT = –2.0 mA) 2.4 — V VOL Output Low Voltage (IOUT = 2.0 mA) — 0.4 V II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –40 40 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT < VCC) –40 40 µA SPD-Table: (Continued) Byte Number Function Described SPD Entry Value Hex Value 100 MHz -10PC |
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