ADS62C15IRGCRG4 datasheet(7/62 Pages) TI

Part #	ADS62C15IRGCRG4

Description	Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

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DIGITAL CHARACTERISTICS

ADS62C15

www.ti.com ........................................................................................................................................................ SLAS577B – JANUARY 2008 – REVISED MAY 2008

ELECTRICAL CHARACTERISTICS (continued)

Typical values at 25

°C, min and max values are across the full temperature range T

MIN = –40°C to TMAX = 85°C, AVDD = 3.3

V, DRVDD = 1.8 V to 3.3 V, sampling frequency = 125 MSPS, 50% clock duty cycle, –1 dBFS differential analog input,

internal reference mode, SNRBoost disabled, applies to CMOS and LVDS interfaces (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

Cross-talk

Cross-talk signal frequency up to 100 MHz

95

dB

For 100 mVPP signal on AVDD supply, frequency up

PSRR

AC Power supply rejection ratio

45

dBc

to 10 MHz

Table 1. SNR Improvement with SNRBoost Sampling Frequency at 125 MSPS (1)(2)

SNR, SIGNAL TO NOISE RATIO (TYP)

dBFS

INPUT FREQUENCY

BANDWIDTH

MHz

SNRBoost disabled, dB

SNRBoost enabled, dB

MIN

TYP

MIN

TYP

5

77

78.1

81

85.1

10

74

75.1

78

82

117

15

72

73.3

76

79.6

20

71

72.1

74.5

77.5

(1)

The min SNR value with SNRBoost enabled is specified by design and characterization; it is not tested in production.

(2)

This table shows the SNR improvement over some selected bandwidths. With SNRBoost, SNR improvement can be achieved for any

bandwidth less than (Sampling frequency/2). As the bandwidths increase, the amount of improvement reduces.

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. AVDD = 3.3 V, DRVDD = 1.8 V to 3.3 V, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS

High-level input voltage

2.4

V

Low-level input voltage

0.8

V

High-level input current

33

µA

Low-level input current

–33

µA

Input capacitance

4

Pf

DIGITAL OUTPUTS – CMOS MODE, DRVDD = 1.8 to 3.3 V

High-level output voltage

DRVDD

V

Low-level output voltage

0

V

Output capacitance (internal to device)

2

pF

DIGITAL OUTPUTS – LVDS MODE(1) (2), DRVDD = 3.3 V

High-level output voltage

1375

mV

Low-level output voltage

1025

mV

|VOD|

Output differential voltage

250

350

500

mV

VOS

Output offset voltage

Common-mode voltage of OUTP and OUTM

1200

mV

Output capacitance inside the device, from

Output Capacitance

2

pF

either output to ground

(1)

LVDS buffer current setting, IO = 3.5 mA.

(2)

External differential load resistance between the LVDS output pairs, RLOAD = 100 Ω.

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