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TAS5414TDKDRQ1G4 Datasheet(PDF) 8 Page - Texas Instruments |
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TAS5414TDKDRQ1G4 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 44 page  www.ti.com ELECTRICAL CHARACTERISTICS TAS5414 TAS5424 SLOS514A – FEBRUARY 2007 – REVISED JULY 2007 Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Rext = 20 kΩ, master mode operation (see application diagram) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING CURRENT IPVDD_IDLE All four channels running in MUTE mode 240 300 PVDD idle current mA IPVDD_Hi-Z All four channels in Hi-Z mode 80 IPVDD_STBY PVDD standby current STANDBY mode, TJ ≤ 85°C 2 20 μA OUTPUT POWER 4 Ω, PVDD = 14.4V, THD+N ≤ 1%, 1 kHz, T c = 75°C 23 4 Ω, PVDD = 14.4V, THD+N = 10%, 1 kHz, T c = 75°C 25 28 4 Ω, PVDD = 14.4V, square wave, 1 kHz, T c = 75°C 43 4 Ω, PVDD = 21 V, THD+N = 1%, 1 kHz, T c = 75°C 47 4 Ω, PVDD = 21 V, THD+N = 10%, 1 kHz, T c = 75°C 50 58 2 Ω, PVDD = 14.4V, THD+N = 1%, 1 kHz, T c = 75°C 38 POUT Output power per channel W 2 Ω, PVDD = 14.4V, THD+N = 10%, 1 kHz, T c = 75°C 40 45 2 Ω, PVDD = 14.4 V, square wave 1 kHz, T c = 75°C 70 PBTL 2- Ω operation, PVDD = 21 V, THD+N = 10%, 116 1 kHz, Tc = 75°C PBTL 1- Ω operation, PVDD = 14.4 V, THD+N = 10%, 90 1 kHz, Tc = 75°C 4 channels operating, 23W output power/ch, L = 10 μH, EFFP Power efficiency 90% TJ ≤ 85°C AUDIO PERFORMANCE VNOISE Noise voltage at output G = 26 dB, zero input, AES17 filter, and A-weighting 60 100 μV Crosstalk Channel crosstalk 1W, G = 26 dB, 1 kHz 60 75 dB CMRR5424 Common-mode rejection ratio (TAS5424) 1 kHz, 1 Vrms referenced to SGND, G = 26 dB 60 75 dB PSRR Power supply rejection ratio G = 26 dB, PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz 60 75 dB THD+N Total harmonic distortion + noise P = 1 W, G = 26 dB, f = 1 kHz, 0 °C ≤ T J ≤ 75°C 0.02% 0.1% 336 357 378 Switching frequency selectable for AM interference fS Switching frequency 392 417 442 kHz avoidance 470 500 530 RAIN Analog input resistance Internal shunt resistance on each input pin 60 80 100 k Ω AC-coupled common-mode input voltage (zero VIN_CM Common-mode input voltage (non-clipping) 1.3 Vrms differential input) VCM_INT Internal common-mode input bias voltage Internal bias applied to IN_M pin 3.25 V 11 12 13 19 20 21 G Voltage gain (VO/VIN) Source impedance = 0 Ω dB 25 26 27 31 32 33 GCH Channel-to-channel variation Any gain commanded –1 0 1 dB tCM Output-voltage common-mode ramping time 35 ms tGAIN Gain ramping time External CMUTE = 330 nF 30 ms PWM OUTPUT STAGE RDSon FET Drain-to-source resistance Not including bond wire resistance, TJ = 25°C 75 95 m Ω VO_OFFSET Output offset voltage Zero input signal and G = 26 dB ±10 ±25 mV PVDD OVER VOLTAGE (OV) PROTECTION VOV PVDD over voltage shutdown 22.1 23.7 26.3 V LOAD DUMP (LD) PROTECTION VLD_SD_SET Load-dump shutdown voltage 26.6 29 32 V VLD_SD_CLEAR Recovery voltage for load-dump shutdown 23.5 26.4 28.4 V PVDD UNDER VOLTAGE (UV) PROTECTION VUV_SET PVDD under voltage shutdown 6.5 7 7.5 V VUV_CLEAR Recovery voltage for PVDD UV 7 7.5 8 V 8 Submit Documentation Feedback |
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