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TMS418169A-60DZR Datasheet(PDF) 3 Page - Texas Instruments |
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TMS418169A-60DZR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 29 page TMS418169A, TMS428169A 1048576 BY 16-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram ( TMS418169A and TMS428169 A) A0 A1 A9 32 16 16 Timing and Control Column - Address Buffers Row - Address Buffers I/O Buffers Data- In Reg. Data- Out Reg. Column Decode Sense Amplifiers R o w D e c o d e 256K Array 256K Array 256K Array 256K Array 256K Array 256K Array DQ0 – DQ15 RAS UCAS W OE LCAS 16 of 32 Selection 32 10 10 10 32 32 operation dual xCAS Two xCAS pins (LCAS and UCAS) are provided to give independent control of the 16 data I/O pins (DQ0 – DQ15), with LCAS corresponding to DQ0 – DQ7 and UCAS corresponding to DQ8 – DQ15. Each xCAS going low enables its corresponding DQx pins. In write cycles, data-in setup and hold times (tDS and tDH) and write-command setup and hold times (tWCS, tCWL, and tWCH) must be satisfied for each individual xCAS to ensure writing into the storage cells of the corresponding DQ pins. Different modes of operation for upper and lower bytes in one cycle are not allowed, such as the example in Figure 1. RAS UCAS LCAS W Delay write Early write Figure 1. Illegal Dual-xCAS Operation |
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