Electronic Components Datasheet Search |
|
ST14C02C-S21 Datasheet(PDF) 5 Page - STMicroelectronics |
|
ST14C02C-S21 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 12 page 5/12 ST14C02C Figure 6. Write Mode Sequences BYTE WRITE DEV SEL BYTE ADDR DATA IN PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2 AI01941 DATA IN N ACK ACK ACK R/W ACK ACK ACK R/W ACK ACK period the receiver pulls the SDA bus low to ac- knowledge the receipt of the 8 data bits. Data Input During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high transi- tion, and the data must change only when the SCL line is low. Memory Addressing To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends 8 bits to the SDA bus line (with the most significant bit first). These bits represent the Device Select Code (7 bits) and a RW bit. The seven most significant bits of the Device Se- lect Code are the Device Type Identifier, according to the I2C bus definition. For the memory device, the seven bits are fixed at 1010000b (A0h), as shown in Table 4. The 8th bit is the read or write bit (RW). This bit is set to ‘1’ for read and ‘0’ for write operations. If a match occurs on the Device Select Code, the cor- responding memory gives an acknowledgment on the SDA bus during the 9th bit time. Write Operations The Multibyte Write mode is selected when the MODE pin is at VIH, and the Page Write mode is selected when MODE pin is at VIL. The MODE pin may be driven dynamically to CMOS input levels. Following a START condition, the master sends a Device Select Code with the RW bit reset to ‘0’. The memory device acknowledges this, and waits for a byte address. The 8-bit byte address allows access within a 256-byte memory address-space. After receipt of the byte address, the device again responds with an acknowledge bit. Byte Write In the Byte Write mode, the master sends one data byte, which is acknowledged by the memory, as shown in Figure 6. The master then terminates the transfer by generating a STOP condition. The Write mode is independent of the state of the MODE pin, as shown in Table 5, which could be left floating if only this mode is to be used. Howev- er this is not a recommended operating mode, as this pin has to be connected to either VIH or VIL to minimize the stand-by current. Multibyte Write For the Multibyte Write mode, the MODE pin must be held at VIH, as shown in Table 5. The Multibyte Write mode can be started from any address in the memory. The master sends one, two, three or four bytes of data, which are each acknowledged by the memory. The transfer is terminated by the master generating a STOP condition. The maxi- mum duration of the write cycle is tW=10 ms (as shown in Table 8), except when bytes span across two rows. (That is, when they have different values for the 6 most significant address bits, A7-A2). The programming time is then doubled to a maximum of 20 ms. Writing more than four bytes in the Multi- |
Similar Part No. - ST14C02C-S21 |
|
Similar Description - ST14C02C-S21 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |