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TYPICAL CHARACTERISTICS

0

2

4

3.5

3

2.5

0

50

100

150

200

225

175

125

75

25

1.5

1

0.5

TB5R3

SLLS643A – SEPTEMBER 2005 – REVISED OCTOBER 2007

TYPICAL PROPAGATION DELAY

vs

LOAD CAPACITANCE

NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the

sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed in the table above as the 0

pF load condition. The incremental increase in delay between the 0 pF load condition and the actual total load capacitance

represents the extrinsic, or external delay contributed by the load.

Figure 5.

6

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