LM3S817 Data Sheet
May 4, 2007
3
Preliminary
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 17
About This Document..................................................................................................................... 18
Audience........................................................................................................................................................... 18
About This Manual............................................................................................................................................ 18
Related Documents .......................................................................................................................................... 18
Documentation Conventions............................................................................................................................. 18
1.
Architectural Overview ....................................................................................................... 21
1.1
Product Features ................................................................................................................................. 21
1.2
Target Applications .............................................................................................................................. 25
1.3
High-Level Block Diagram ................................................................................................................... 26
1.4
Functional Overview ............................................................................................................................ 27
1.4.1
ARM Cortex™-M3 ............................................................................................................................... 27
1.4.2
Motor Control Peripherals .................................................................................................................... 27
1.4.3
Analog Peripherals .............................................................................................................................. 28
1.4.4
Serial Communications Peripherals..................................................................................................... 28
1.4.5
System Peripherals.............................................................................................................................. 29
1.4.6
Memory Peripherals............................................................................................................................. 30
1.4.7
Additional Features.............................................................................................................................. 30
1.4.8
Hardware Details ................................................................................................................................. 31
1.5
System Block Diagram ........................................................................................................................ 32
2.
ARM Cortex-M3 Processor Core........................................................................................ 33
2.1
Block Diagram ..................................................................................................................................... 34
2.2
Functional Description ......................................................................................................................... 34
2.2.1
Serial Wire and JTAG Debug .............................................................................................................. 34
2.2.2
Embedded Trace Macrocell (ETM) ...................................................................................................... 35
2.2.3
Trace Port Interface Unit (TPIU) .......................................................................................................... 35
2.2.4
ROM Table .......................................................................................................................................... 35
2.2.5
Memory Protection Unit (MPU) ............................................................................................................ 35
2.2.6
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 35
3.
Memory Map ........................................................................................................................ 41
4.
Interrupts ............................................................................................................................. 43
5.
JTAG Interface .................................................................................................................... 46
5.1
Block Diagram ..................................................................................................................................... 47
5.2
Functional Description ......................................................................................................................... 47
5.2.1
JTAG Interface Pins............................................................................................................................. 48
5.2.2
JTAG TAP Controller ........................................................................................................................... 49
5.2.3
Shift Registers ..................................................................................................................................... 50
5.2.4
Operational Considerations ................................................................................................................. 50
5.3
Initialization and Configuration............................................................................................................. 51
5.4
Register Descriptions........................................................................................................................... 52
5.4.1
Instruction Register (IR) ....................................................................................................................... 52
5.4.2
Data Registers ..................................................................................................................................... 54