LM3S815 Data Sheet
April 28, 2007
3
Preliminary
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 18
About This Document..................................................................................................................... 20
Audience........................................................................................................................................................... 20
About This Manual............................................................................................................................................ 20
Related Documents .......................................................................................................................................... 20
Documentation Conventions............................................................................................................................. 20
1.
Architectural Overview ....................................................................................................... 23
1.1
Product Features ................................................................................................................................. 23
1.2
Target Applications .............................................................................................................................. 27
1.3
High-Level Block Diagram ................................................................................................................... 28
1.4
Functional Overview ............................................................................................................................ 29
1.4.1
ARM Cortex™-M3 ............................................................................................................................... 29
1.4.2
Motor Control Peripherals .................................................................................................................... 29
1.4.3
Analog Peripherals .............................................................................................................................. 30
1.4.4
Serial Communications Peripherals..................................................................................................... 30
1.4.5
System Peripherals.............................................................................................................................. 31
1.4.6
Memory Peripherals............................................................................................................................. 32
1.4.7
Additional Features.............................................................................................................................. 33
1.4.8
Hardware Details ................................................................................................................................. 33
1.5
System Block Diagram ........................................................................................................................ 34
2.
ARM Cortex-M3 Processor Core........................................................................................ 35
2.1
Block Diagram ..................................................................................................................................... 36
2.2
Functional Description ......................................................................................................................... 36
2.2.1
Serial Wire and JTAG Debug .............................................................................................................. 36
2.2.2
Embedded Trace Macrocell (ETM) ...................................................................................................... 37
2.2.3
Trace Port Interface Unit (TPIU) .......................................................................................................... 37
2.2.4
ROM Table .......................................................................................................................................... 37
2.2.5
Memory Protection Unit (MPU) ............................................................................................................ 37
2.2.6
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 37
3.
Memory Map ........................................................................................................................ 43
4.
Interrupts ............................................................................................................................. 45
5.
JTAG Interface .................................................................................................................... 48
5.1
Block Diagram ..................................................................................................................................... 49
5.2
Functional Description ......................................................................................................................... 49
5.2.1
JTAG Interface Pins............................................................................................................................. 50
5.2.2
JTAG TAP Controller ........................................................................................................................... 51
5.2.3
Shift Registers ..................................................................................................................................... 52
5.2.4
Operational Considerations ................................................................................................................. 52
5.3
Initialization and Configuration............................................................................................................. 53
5.4
Register Descriptions........................................................................................................................... 54
5.4.1
Instruction Register (IR) ....................................................................................................................... 54
5.4.2
Data Registers ..................................................................................................................................... 56
6.
System Control.................................................................................................................... 58
6.1
Functional Description ......................................................................................................................... 58
6.1.1
Device Identification............................................................................................................................. 58