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ST24LC21B1TR Datasheet(PDF) 11 Page - STMicroelectronics |
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ST24LC21B1TR Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 18 page  After each byte is transfered, the internal byte address counter (3 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter ’roll-over’ which could result in data being overwritten. Note that, for any write mode, the generation by the master of the STOP condition starts the internal memory pro- gram cycle. All inputs are disabled until the comple- tion of this cycle and the memory will not respond to any request. Minimizing System Delays by Polling On ACK. During the internal write cycle, the memory discon- nects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (tW) is given in the AC Characteristics table, since the typical time is shorter, the time seen by the system may be re- duced by an ACK polling sequence issued by the master. The sequence is as follows: – Initial condition: a Write is in progress (see Figure 9). – Step 1: the Master issues a START condition followed by a Device Select byte (1st byte of the new instruction). – Step 2: if the memory is busy with the internal write cycle, no ACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it will respond with an ACK, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction was already sent during Step 1). WRITE Cycle in Progress AI01099B Next Operation is Addressing the Memory START Condition DEVICE SELECT with RW = 0 ACK Returned YES NO YES NO ReSTART STOP Proceed WRITE Operation Proceed Random Address READ Operation Send Byte Address First byte of instruction with RW = 0 already decoded by ST24xxx Figure 9. Write Cycle Polling using ACK DEVICE OPERATIONS (cont’d) 11/18 ST24LC21 |
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