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TMS320DM6431 Datasheet(PDF) 1 Page - Texas Instruments

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Part # TMS320DM6431
Description  Digital Media Processor
Download  226 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM6431 Datasheet(HTML) 1 Page - Texas Instruments

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TMS320DM6431 Digital Media Processor
1.1 Features
TMS320DM6431
Digital Media Processor
www.ti.com
SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008
• High-Performance Digital Media Processor
• C64x+ L1/L2 Memory Architecture
(DM6431)
256K-Bit (32K-Byte) L1P Program
3.33-ns Instruction Cycle Time
RAM/Cache [Flexible Allocation]
300-MHz C64x+™ Clock Rate
512K-Bit (64K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
Eight 32-Bit C64x+ Instructions/Cycle
512K-Bit (64K-Byte) L2 Unified Mapped
2400 MIPS
RAM/Cache [Flexible Allocation]
Fully Software-Compatible With C64x
• Supports Little Endian Mode Only
Commercial and Automotive (Q or S suffix)
Grades
• Video Processing Subsystem (VPSS), VPFE
Only
• VelociTI.2™ Extensions to VelociTI™
Front End Provides:
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
• CCD and CMOS Imager Interface
Eight Highly Independent Functional Units
• BT.601/BT.656 Digital YCbCr 4:2:2
With VelociTI.2 Extensions:
(10-Bit) Interface
• Six ALUs (32-/40-Bit), Each Supports
• Glueless Interface to Common Video
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Decoders
Arithmetic per Clock Cycle
• External Memory Interfaces (EMIFs)
• Two Multipliers Support Four 16 x 16-Bit
16-Bit DDR2 SDRAM Memory Controller
Multiplies (32-Bit Results) per Clock
With 128M-Byte Address Space (1.8-V I/O)
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
• Supports up to 266-MHz (data rate) bus
Results) per Clock Cycle
and interfaces to DDR2-400 SDRAM
Load-Store Architecture With Non-Aligned
Asynchronous 8-Bit Wide EMIF (EMIFA)
Support
With up to 64M-Byte Address Reach
64 32-Bit General-Purpose Registers
• Flash Memory Interfaces
Instruction Packing Reduces Code Size
NOR (8-Bit-Wide Data)
All Instructions Conditional
NAND (8-Bit-Wide Data)
Additional C64x+™ Enhancements
• Enhanced Direct-Memory-Access (EDMA)
• Protected Mode Operation
Controller (64 Independent Channels)
• Exceptions Support for Error Detection
• Two 64-Bit General-Purpose Timers (Each
and Program Redirection
Configurable as Two 32-Bit Timers)
• Hardware Support for Modulo Loop
• One 64-Bit Watch Dog Timer
Auto-Focus Module Operation
• One UART With RTS and CTS Flow Control
• C64x+ Instruction Set Features
Byte-Addressable (8-/16-/32-/64-Bit Data)
• Master/Slave Inter-Integrated Circuit (I2C
8-Bit Overflow Protection
Bus™)
Bit-Field Extract, Set, Clear
• One Multichannel Buffered Serial Port
Normalization, Saturation, Bit-Counting
(McBSP0)
VelociTI.2 Increased Orthogonality
I2S and TDM
C64x+ Extensions
AC97 Audio Codec Interface
• Compact 16-bit Instructions
SPI
• Additional Instructions to Support
Standard Voice Codec Interface (AIC12)
Complex Multiplies
Telecom Interfaces – ST-Bus, H-100
128 Channel Mode
• Multichannel Audio Serial Port (McASP0)
Four Serializers and SPDIF (DIT) Mode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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