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CAT5409 Datasheet(PDF) 1 Page - Catalyst Semiconductor

Part # CAT5409
Description  Quad Digitally Programmable Potentiometers (DPP?? with 64 Taps and I짼C Interface
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Manufacturer  CATALYST [Catalyst Semiconductor]
Direct Link  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT5409 Datasheet(HTML) 1 Page - Catalyst Semiconductor

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CAT5409
© Catalyst Semiconductor, Inc.
1
Doc. No. MD-2010 Rev. K
Characteristics subject to change without notice
Quad Digitally Programmable Potentiometers
(DPP™) with 64 Taps and I²C Interface
FEATURES
Four linear taper digitally programmable
potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
I²C interface
Low wiper resistance, typically 80Ω
Four non-volatile wiper settings for each
potentiometer
Recall of saved wiper settings at power-up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Write protection for data register
For Ordering Information details, see page 15.
PIN CONFIGURATION
SOIC (W)
TSSOP (Y)
DESCRIPTION
The
CAT5409
is
four
Digitally
Programmable
Potentiometers (DPP™) integrated with control logic
and 16 bytes of NVRAM memory.
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DPP.
Associated with each wiper control register are four
6-bit non-volatile memory data registers (DR) used for
storing up to four wiper settings. Writing to the wiper
control register or any of the non-volatile data
registers is via a I²C serial bus. On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control register (WCR).
The Write Protection (WP
¯¯¯) pin protects against
inadvertent programming of the data register.
The CAT5409 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
FUNCTIONAL DIAGRAM
2
23
RL0
RL3
322
RH0
RH3
124
VCC
NC
4
RW0
RW3
21
A0
A2 520
NC
619
WP
A1
SCL
8
17
RL1
RL2
916
A3
718
SDA
RH1
RH2
10
15
RW1
RW2
11
14
GND
NC
12
13
2
23
RL0
RL3
322
RH0
RH3
124
VCC
4
RW0
RW3
21
A0
A2
520
NC
619
WP
A1
SCL
8
17
RL1
RL2
916
A3
718
SDA
RH1
RH2
10
15
RW1
RW2
NC
11
14
GND
NC
12
13
NONVOLATILE
DATA
REGISTERS
CONTROL LOGIC
WIPER CONTROL
REGISTERS
I²C BUS
INTERFACE
RW0
RW1
RW2
RW3
RL0
A0
A1
A2
A3
SCL
SDA
RL1
RL2
RL3
RH0
RH1
RH2
RH3
WP


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