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ST72260G Datasheet(PDF) 20 Page - STMicroelectronics |
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ST72260G Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 171 page  ST72260G, ST72262G, ST72264G 20/171 6 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. An overview is shown in Figure 10. For more details, refer to dedicated parametric section. Main Features s Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator) s Reset Sequence Manager (RSM) s Multi-Oscillator Clock Management (MO) – 4 Crystal/Ceramic resonator oscillators – 1 Internal RC oscillator s System Integrity Management (SI) – Main supply Low Voltage Detector (LVD) – Auxiliary Voltage Detector (AVD) with inter- rupt capability for monitoring the main supply – Clock Security System (CSS) with Clock Filter and Backup Safe Oscillator (enabled by op- tion byte) 6.1 PHASE LOCKED LOOP If the clock frequency input to the PLL is in the 2 to 4 MHz range, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2. Caution: The PLL is not recommended for appli- cations where timing accuracy is required. See “PLL Characteristics” on page 134. Figure 9. PLL Block Diagram Figure 10. Clock, Reset and Supply Block Diagram 0 1 PLL OPTION BIT PLL x 2 fOSC2 / 2 fOSC LOW VOLTAGE DETECTOR (LVD) fOSC2 AUXILIARY VOLTAGE DETECTOR (AVD) MULTI- OSCILLATOR (MO) OSC1 RESET VSS VDD RESET SEQUENCE MANAGER (RSM) CLOCK FILTER SAFE OSC CLOCK SECURITY SYSTEM (CSS) OSC2 MAIN CLOCK CSS Interrupt Request AVD Interrupt Request CONTROLLER PLL SYSTEM INTEGRITY MANAGEMENT WATCHDOG SICSR TIMER (WDG) WITH REALTIME CLOCK (MCC/RTC) AVD AVD LVD RF CSS IE IE CSS D WDG RF fOSC fOSC2 (option) 0 F fCPU 0 |
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