Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.NET

X  

Preview PDF Download HTML

ST7285C Datasheet(HTML) 70 Page - STMicroelectronics

Part No. ST7285C
Description  8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
Download  117 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo 

ST7285C Datasheet(HTML) 70 Page - STMicroelectronics

Zoom Inzoom in Zoom Outzoom out
Go To Page :
/ 117 page
background image
70/117
ST7285C
RDS DEMODULATOR (Cont’d)
RDS DE1
Address 005C h
Reset Value: 0000 0000b
b7 = lock
Inhibits regulation of PLLs to keep the current
phase value during weak signal conditions.
0: normal regulation (Reset Value)
1: inhibit regulation.
b6-5 = lck3 - lck2
Select time constant for 1187.5Hz PLL.
b4-3 = lck1 - lck0
Select time constant of 57KHz PLL.
b2 = QEN
Enables automatic selection of input to differential
decoder 1.
0 = enable selection by quality (Reset Value)
1 = disable selection
b1 = SDAT
Selects differential decoder for the RDS data output.
0 = differential decoder 1 (Reset Value)
1 = differential decoder 2.
b0 = SQUAL
Selects quality for the quality output.
0 = from the quality detector (qal1) (Reset Value)
1 = exclusive OR of differential decoders (qal2).
RDS DE2
Address 005D h
Reset Value: 0xxx xxxx b
b7 = UPR
Software reset to various demodulator parts.
0 = normal run mode (Reset Value)
1 = demodulator reset.
After wring this bit to one, a reset pulse will be gen-
erated. The bit will then be automatically reset to
zero. This bit is always read as a zero.
b6 = QAL
Output of the quality detector which is actually de-
tected. This bit is fed into the RDS-GBS module.
b5 = QAL1
Output of the quality detector.
b4 = QAL2
Resulant of XOR of dat1 and dat2.
b3 = DAT
RDS-dat output which is actually detected. This bit
is fed into the RDS-GBS module.
b2 = DAT1
Output of the phase polarity data extractor.
b1 = DAT2
Output of the phase integral data extractor.
b0 = CLK
RDS clock output (1187.5Hz)
7
654321
0
lock
lck3
lck2
lck1
lck0
qen
sdat
squal
lck3
lck2
lock time needed for max (90
°)
deviation
0
0
160ms (Reset Value)
0
1
80ms
1
0
40ms
1
1
20ms
lck1
lck0
lock time needed for max (90
°)
deviation
0
0
16ms(Reset Value)
0
1
8ms
1
0
4ms
1
1
2ms
70
UPR
QAL
QAL1
QAL2
DAT
DAT1
DAT2
CLK


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download




Link URL



Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Bookmark   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn