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ST7285C Datasheet(HTML) 74 Page - STMicroelectronics

Part No. ST7285C
Description  8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST7285C Datasheet(HTML) 74 Page - STMicroelectronics

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ST7285C
RDS G.B.S. (Cont’d)
4.9.3 Functional Description
4.9.3.1 Principles of Baseband Coding
Figure 34 illustrates the principles of baseband
coding. The largest element in the structure is
called a “group”. Each group contains 4 blocks of
26 bits each. Each block contains an information
word (16 bits) and a check-word (10bits).
The basic baseband data rate e is 1187.5 bits/s.
The baseband is a modified shortened cyclic code,
that means the transmitted vector c(x) is given by:
c(x) = d(x) +m(x)
*x
10 + {m(x)
*x
10}/d(x) |
mod g(x)
where, m(x) represents the 16-bit message vector:
m(x) = m
15*x
15 +m
14*x
14 +...+ m
1*x
1 +m
0*x
0
g(x) represents the polynomial generator:
g(x) = x
10 +x8 +x7 +x5 +x4 +x3 +1
and d(x) represents the offset word according to
the values tabulated in Table 9 below.
For more information about the theory and imple-
mentation of the modified shortened cyclic code,
please refer to the specification of the European
Broadcasting Union.
4.9.3.2 Hardware Configuration
The GBS circuit comprises the following functional
blocks; these are shown schematically in the Block
Diagram, Figure 35.
– 26-bit Shift Register (SR3- SR0), may act, either
as a straight 26-bit delay or as a recirculating shift
register. On each rising edge of RDSCLK a new
RDS-bit is shifted into the register. Then, the con-
tents of the shift register are rotated 26 times (one
circuit) for syndrome calculation.
In error correction mode (ECM=1), the shift reg-
ister acts only as a circular register. New RDS-bits
are not shifted in. They are stored in the parallel
shift register DR0- DR3.
– Polynomial Division circuit, comprising a 10-bit
shift register (SY0- SY1) with feedback taps for
syndrome calculation. During the rotation of the
shift register the RDS-bits are passed serially
into the polynomial division register where the
syndrome is calculated and stored.
– Syndrome Detection circuit, compares the cal-
culated syndrome with a 5(6)-word syndrome
ROM. The output consists of the block code
BL[2:0] and the VSI flag with its associated inter-
rupt. VSI is high when a valid syndrome is detect-
ed. Detection of offset syndrome, E, is enabled
by control bit US.
– 5-bit Counter (CNA), counts down on every rising
edge of RDSCLK. The counter reload register can
be written by software. On zero count, it restarts
immediately with the value of the reload register
and can generate an interrupt on zero count. This
counter is used as RDS-bit counter (26...1).
– 2-bit Counter (CNB), counts down on every zero
count of CNA. The counter can be written by soft-
ware. CNB is running free and can generate an
interrupt. This counter is used as RDS-block
counter (3...1)
– Timing Generator block comprising a modulo-
28 counter with end stops and some combina-
tional logic. The modulo-28 counter is used to
generate one shift clock, 26 rotate clocks and
one end of calculation clock. In error correction
mode (ECM=1) the shift clock is masked.
– 26-bit RDSDAT register (DR3-DR0), in parallel
to shift register SR3-SR1. It works in straight shift
mode only. On each rising edge of the RDSCLK
the RDSDAT-bit is shifted into the register. This
register is used for temporary block storage dur-
ing error correction.
– 26-bit QUALITY register (QR3-QR0), works in
straight shift mode only. On each rising edge of
the RDSCLK the QUALITY bit coming from the
demodulator is shifted into the register.
Table 9. Offset Words and their corresponding Syndromes
Offset
(block)
Block code
BL
2 BL1 BL0
Offset word
d9,d8,d7,...,d0
Syndrome
d9,d8,d7,...,d0
A
0 1 0
0011111100
1111011000
B
0 0 1
0110011000
1111010100
C
1 0 0
0101101000
1001011100
C’
0 0 0
1101010000
1111001100
D
0 1 1
0110110100
1001011000
E
1 0 1
0000000000
0000000000
WRONG
1 1 1
all others
all others


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