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ST7285C Datasheet(PDF) 76 Page - STMicroelectronics |
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ST7285C Datasheet(HTML) 76 Page - STMicroelectronics |
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76 / 117 page  76/117 ST7285C RDS G.B.S. (Cont’d) GS_CNT - Count Register b7-6 = CNB[1;0] free-running 2-bit counter; used as block/order counter. It is decremented on zero- count of CNA[4:0]. The zero-counts of CNA and CNB are used for counter interrupt generation. Re- set Value equals one. b5 = SYNC: Set to “1” whenever CNA[4;0] reach- es a zero-count. it is valid for one period of RDSCLK. Read only. SYNC flag is used when a counter interrupt is desired on every RDSCLK (used for general timing or ARI filter service), while the BLK-SYNC interrupt service is performed eve- ry 26 bits (CNA=26). b4-0 = CNA[4:0]: 5-bit r/w autoreload counter; used as RDS bit counter. It is decremented on every rising edge of RDSCLK. When writing to CNA, both a latch and the counter itself are writ- ten. Immediately after reaching zero-count, the contents of the latch are loaded back into the counter (autoreload), so the zero-count state can never be read by software. The zero-count of CNA is used for counter interrupt generation. Reset Val- ue equals one. GS_INT - Interrupt Register b7 = CAL: Start Calculation. Writing a “1” into CAL leads to a new syndrome calculation. CAL is al- ways read as “0”. Used in software error correc- tion. b6 = CAR: Calculation Running. Set to “1” by writ- ing CAL=1. It returns to “0” when the syndrome calculation is complete (VSI valid). Read only. Used in software error correction. b5 = ECM: Error Correction Mode. If error correc- tion by software is to be performed, ECM must be set to “1”. This suppresses both shift and rotate clocks for shift registers SR3-SR0, making them available for software-triggered syndrome calcula- tions which may require more than one RDSCLK period. On completion of a correction, ECM must be reset to “0” and the current status of SR3-SR0 must be retrieved from the shadow registers DR3- DR0 by a copy routine. b4 = VSI: Valid Syndrome Interrupt. This flag is set to “1” when the block code (BL[2:0]) is equal to one of the six valid syndromes. Otherwise, it is reset to “0”. VSI is valid on completion of a syndrome cal- culation, for one period of RDSCLK. However, VSI must be reset by software at the end of the inter- rupt service routine. VSI and CNI interrupts are ORed to the active-high level interrupt, ITSYNC. b3 = VSE: Valid Syndrome interrupt Enable. Set- ting VSE to “1” enables the VSI interrupt. b2 = CNI: Counter Interrupt. This flag is set to “1”on the zero-count of CNA/CNB or on the rising edge of RDSCLK, depending on the setting of CNE[1:0]. CNI is valid on completion of the syn- drome calculation, for one period of RDSCLK. However, CNI must be reset by software at the end of the interrupt service routine. VSI and CNI interrupts are ORed to the active high level inter- rupt ITSYNC. b1,0 = CNE[1:0]. Enables and selects the counter interrupt, see Table 11 below: Table 11. Counter Interrupt Source Selection DR0 - RDSDAT Register 0 b7,6 = DR[1:0]. Receives RDSDAT sequence. b5 = reserved, always read as “0”. b4 = MQE: Multiple Quality Error. Set to “1” when 2 or more low quality bit are detected during the last block (26 bits). MQE is valid for one period of RDSCLK, starting with CNA zero-count and is re- set by hardware at the end of this period. b3 = SQE: Single Quality Error. Set to “1” when a low quality bit is detected during the last block (26 bits). SQE is valid for one period of RDSCLK, starting with CNA zero-count and is reset by hard- ware at the end of this period. b2 = QAL. Transparent QUALITY input signal from RDS demodulator; read only. b1 = RCL. Transparent RDSCLK input signal from RDS demodulator; read only. b0 = RDA. Transparent RDSDAT input signal from RDS demodulator; read only. DRx - RDS Data Registers DR1. b7-0 contain bits 9-2 of a received RDSDAT sequence. DR2. b7-0 contain bits 17-10 of a received RDS- DAT sequence. DR3. b7-0 contain bits 18-25 of a received RDS- DAT sequence. CNE1 CNE0 Counter Interrupt Source Selection 0 0 counter interrupt disabled 01 counter interrupt on every rising edge of RDSCLK 10 counter interrupt on CNA zero-count state 11 counter interrupt on CNA & CNB zero count states |
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