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ST7285C Datasheet(HTML) 13 Page - STMicroelectronics

Part No. ST7285C
Description  8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST7285C Datasheet(HTML) 13 Page - STMicroelectronics

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ST7285C
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU has a full 8-bit architecture. Six internal
registers allow efficient 8-bit data manipulation.
The CPU is capable of executing 63 basic instruc-
tions and features 17 main addressing modes.
2.2 CPU REGISTERS
The 6 CPU registers are shown in the program-
ming model in Figure 2. Following an interrupt, all
registers except Y are pushed onto the stack in the
order shown in Figure 3. They are popped from
stack in the reverse order.
Accumulator (A). The Accumulator is an 8-bit
general purpose register used to hold operands
and the results of the arithmetic and logic calcula-
tions as well as data manipulations.
Index Registers (X and Y). These 8-bit registers
are used to create effective addresses or as tem-
porary storage areas for data manipulation. The
Cross-Assembler generates a PRECEDE instruc-
tion (PRE) to indicate that the following instruction
refers to the Y register. The Y register is never au-
tomatically stacked. Interrupt routines must push
or pop it by using the PUSH and POP instructions.
Program Counter (PC). The program counter is a
16-bit register containing the address of the next
instruction to be executed by the CPU.
Figure 2. Organization of Internal CPU Registers
ACCUMULATOR:
X INDEX REGISTER:
Y INDEX REGISTER:
PROGRAM COUNTER:
STACK POINTER:
CONDITION CODE REGISTER:
X = Undefined
RESET VALUE:
70
XX
X XXXX X
RESET VALUE:
70
XX
X XXXX X
RESET VALUE:
70
XX
XX XX X X
15
70
RESET VALUE = DEVICE DEPENDENT, SEE MEMORY MAP
RESET VALUE:
70
XX
XXX XXX
15
70
RESET VALUE = DEVICE DEPENDENT, SEE MEMORY MAP


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