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ST7285C Datasheet(HTML) 14 Page - STMicroelectronics

Part No. ST7285C
Description  8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST7285C Datasheet(HTML) 14 Page - STMicroelectronics

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ST7285C
CPU REGISTERS (Cont’d)
Stack Pointer (SP) The Stack Pointer is a 16-bit
register. Since the stack size can vary from device
to device, the appropriate number of most signifi-
cant bits are forced so as to map the stack as de-
fined in the Memory Map. The number of least sig-
nificant digits thus available to the user will depend
on the stack size, for example in the case of a 128
byte stack, 7 bits will be available whereas in the
case of a 64 byte stack, only 6 bits will be available.
The stack is used to save the CPU context during
subroutine calls or interrupts. The user may also
directly manipulate the stack by means of the
PUSH and POP instructions.
Following an MCU Reset, or after a Restore fol-
lowing a Reset Stack Pointer instruction (RSP),
the Stack Pointer is set to point to the highest loca-
tion in the stack. It is then decremented after data
has been pushed onto the stack and incremented
after data is popped from the stack. When the low-
er limit is exceeded, the Stack Pointer wraps
around to the stack upper limit. The previously
stored information is then overwritten and there-
fore lost. The upper and lower limits of the stack
area are shown in the Memory Map.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Condition Code Register (CC) The Condition
Code register is a 5-bit register which indicates the
result of the instruction just executed as well as the
state of the processor. These bits can be individu-
ally tested by a program and specified action taken
as a result of their state. The following paragraphs
describe each bit of the CC register in turn.
Half carry bit (H) The H bit is set to 1 when a carry
occurs between bits 3 and 4 of the ALU during an
ADD or ADC instruction. The H bit is useful in BCD
arithmetic subroutines.
Interrupt mask (I) When the I bit is set to 1, all in-
terrupts except the TRAP software interrupt are
disabled. Clearing this bit enables interrupts to be
passed to the processor core. Interrupts requested
while I is set are latched and can be processed
when I is cleared (only one interrupt request per in-
terrupt enable flag can be latched).
Negative (N) When set to 1, this bit indicates that
the result of the last arithmetic, logical or data ma-
nipulation is negative (i.e. the most significant bit is
a logic 1).
Zero (Z) When set to 1, this bit indicates that the
result of the last arithmetic, logical or data manipu-
lation is zero.
Carry/Borrow (C) When set, C indicates that a
carry or borrow out of the ALU occured during the
last arithmetic operation. This bit is also affected
during execution of bit test, branch, shift, rotate
and store instructions.
Figure 3. Stacking Order
INCREASING
MEMORY
UNSTACK
ACCUMULATOR
X INDEX REGISTER
PCH
PCL
(PUSH)
DECREASING
MEMORY
11
1
VR000074
0
7
ADDRESSES
ADDRESSES
STACK
(POP)
CONDITION CODE


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