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ST7285C Datasheet(HTML) 23 Page - STMicroelectronics

Part No. ST7285C
Description  8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST7285C Datasheet(HTML) 23 Page - STMicroelectronics

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ST7285C
POWER SAVING MODES (Cont’d)
3.6.3 Halt Mode
The HALT instruction places the MCU in its lowest
power consumption mode. In HALT mode the in-
ternal oscillator is turned off, causing all internal
processing to be halted. During HALT mode, the I
bit in the CC Register is cleared so as to enable
External Interrupts.
All other registers and memory remain unaltered
and all Input/Output lines remain unchanged. This
state will endure until an External Interrupt (I1, I2,
I9, I10) or a Reset is generated, whereupon the in-
ternal oscillator is restarted. A delay of 4096 CPU
clock cycles is initiated prior to restarting the appli-
cation, in order to allow the oscillator to stabilize.
The External Interrupt or Reset causes the Pro-
gram Counter to be set to the address of the corre-
sponding Interrupt or Reset Service Routine.
Figure 12. Halt Mode Flow Chart
N
Y
VR02062E
N
EXTERNAL
INTERRUPT
WAIT
HALT
Y
STOP OSCILLATOR
AND ALL CLOCKS
CLEAR I-BIT
RESET
OSCILLATOR
IN SLOW MODE
TURN ON
OSCILLATOR
WAIT FOR 4096 CPU
CLOCK TIME DELAY
FETCH RESET
VECTOR OR
SERVICE INTERRUPT


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