Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.NET

X  

Preview PDF Download HTML

ST7285C Datasheet(HTML) 42 Page - STMicroelectronics

Part No. ST7285C
Description  8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
Download  117 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo 

ST7285C Datasheet(HTML) 42 Page - STMicroelectronics

Zoom Inzoom in Zoom Outzoom out
Go To Page :
/ 117 page
background image
42/117
ST7285C
16-BIT TIMER (Cont’d)
4.3.5.2 Forced Compare Mode
The main purpose of the Forced Compare mode is
to facilitate fixed frequency generation.
In this section
i may represent 1 or 2.
When the Forced Output Level
i bit (FOLVi)of
TCR1 is written to 1, OLVL
i is copied to the OCMPi
pin. To provide this capability, internal logic allows
a single instruction to change OLVL
i and causes a
forced compare with the new value of OLVL
i.OCFi
is not affected, and thus no interrupt request is
generated.
4.3.5.3 One Pulse Mode
The One Pulse mode enables the generation of a
pulse on the occurence of an external event and is
programmed via the OPM bit in the TCR2 register.
The trigger event is applied to the Input Capture1
pin (ICAP1); the active edge of the event is flagged
by the IEDG1 bit in TCR1.
Then, on an event on ICAP1, the counter is initial-
ized to FFFCh and OLVL2 is loaded on the output
compare 1 pin (OCMP1); when the value of the
counter is equal to the value of the contents of
OCR1, the OLVL1 bit is output on the Output Com-
pare 1 pin (OCMP1). No interrupt is generated.
(See Figure 9).
4.3.5.4 Pulse Width Modulation Mode
This mode is similar to the One Pulse mode, in
which the external event is replaced by the Output
Compare 2 event; this mode is programmed via
the PWM bit in the TCR2 register.
OCR1 then contains the length of the pulse, while
OCR2 contains the value of the period; the Output
Compare 2 event causes the counter to be initial-
ized to FFFCh (See Figure 10). No interrupt is
generated
Figure 25. One Pulse Mode Timing, IEDG1=1; OCR1=2ED0h
Figure 26. Pulse Width Modulation Mode Timing, OCR1=2ED0h, OCR2=34E2
COUNTER
....
FFFC FFFD FFFE
2ED0
2ED1 2ED2
2ED3
FFF C FFFD
OLVL2
OLVL2
OLVL1
ICAP1
OCMP1
compare1
COUNTER
34E2
FFFC FFFD FFFE
2ED0 2ED1 2ED2
34E2
FFFC
OLVL2
OLVL2
OLVL1
OCMP1
compare2
compare1
compare2


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Download




Link URL



Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Bookmark   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn