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ST7285C Datasheet(HTML) 53 Page - STMicroelectronics

Part No. ST7285C
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com

ST7285C Datasheet(HTML) 53 Page - STMicroelectronics

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4.4.9 Serial Peripheral Data I/O Register (SPDR)
Address: see Memory Map
Reset Value: XXh
The Serial Peripheral Data I/O Register is used to
transmit and receive data on the serial bus. Only a
write to this register will initiate transmission/re-
ception of another byte and this will only occur in
the Master device. A Slave device writing to its
data I/O register will not initiate a transmission. Af-
ter having transmitted a byte of data, the SPIF sta-
tus bit is set in both the Master and Slave devices.
A write or read of the Serial Peripheral Data I/O
Register, after accessing the Serial Peripheral
Status Register with SPIF set, will clear SPIF.
During the clock cycle the SPIF bit is being set, a
copy of the received data byte in the shift register
is being moved to a buffer. When the user reads
the Serial Peripheral Data I/O Register, the buffer
is actually being read. During an overrun condi-
tion, when the Master device has sent several
bytes of data and the Slave device has not inter-
nally responded to clear the first SPIF, only the
first byte is contained in the receive buffer of the
Slave device; all others are lost. The user may
read the buffer at any time. The first SPIF must be
cleared by the time a second transfer of data from
the shift register to the read buffer is initiated, oth-
erwise an overrun condition will exist.
A write to the Serial Peripheral Data I/O Register is
not buffered, and data is placed directly in the shift
register for transmission.
The ability to access the Serial Peripheral Data I/O
Register is limited when a transmission is taking
place. Please refer to the description of the WCOL
and SPIF status bits in order to fully appreciate the
rules governing the use of the Serial Peripheral
Data I/O Register.
There are two types of SPI systems, single Master
and Multimaster.
A typical Single Master system may be configured,
using one MCU as the Master and four others as
Slaves. The MOSI, MISO and SCK pins are all
wired to equivalent pins on each device. The Mas-
ter device generates the SCK clock, whereas the
Slave devices all receive it. Since the MCU Master
device is the bus Master, it internally controls the
function of its MOSI and MISO lines, thus writing
data to the Slave devices on the MOSI and read-
ing data from the Slave devices on the MISO lines.
The Master device selects the individual Slave de-
vices by using four pins of a parallel port to control
the four SS pins of the Slave devices. A Slave de-
vice is selected when the Master device pulls its
SS pin low. The SS pins are pulled high, thus dis-
abling the Slave devices during Reset, since the
Master device ports will be forced as inputs.
Note that Slave devices need not be enabled in a
mutually exclusive fashion, except in order to pre-
vent bus contention on the MISO lines. An exam-
ple of this is a write to several display drivers to
clear a display using a single I/O operation.
To ensure that proper data transmission takes
place between the Master device and a Slave de-
vice, the Master device may ask the Slave device
to respond by echoing a previously received data
byte (this data byte can be inverted, or at least be
different from the last one sent by the Master de-
vice). The Master device will always receive the
previous byte back from the Slave if all MISO and
MOSI lines are connected and the Slave has not
written its data I/O register. Other transmission se-
curity methods may be defined using ports as
handshake lines, or by means of data bytes con-
taining command fields.
A Multimaster system may also be configured by
the user. An exchange of Master control can be
implemented by adopting a handshake scheme
using the I/O ports, or by an exchange of code
messages via the Serial Peripheral Interface sys-
tem. The principal device controls are the MSTR
bit in the Serial Peripheral Control Register and
the MODF bit in the Serial Peripheral Status Reg-

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