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ST7285C Datasheet(HTML) 56 Page - STMicroelectronics

Part No. ST7285C
Description  8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST7285C Datasheet(HTML) 56 Page - STMicroelectronics

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ST7285C
I
2C BUS INTERFACE (Cont’d)
4.5.4
EPROM/ROM
I C
COMPATIBILITY
APPLICATION NOTE
In order to insure full compatibility between the
EPROM and the ROM versions of the ST7285 mi-
crocontroller, certain timing conditions have to be
respected when using the I
2C interface.
Otherwise the I
2C interface of the ST72E85 can:
– Detect an unexpected START or STOP condi-
tion with BUS ERROR detection
– Generate unexpected BTF flag settings
Unexpected START or STOP condition detec-
tion
In the ST72E85 device, due to the synchronisation
between
the
I
2C peripheral and the f
CPU
(4.332MHz), an unexpected START or STOP con-
dition can be detected in Slave mode. This gener-
ates an unexpected Bus Error and sets the BERR
bit in the SR2 register.
To avoid this effect, the following I C timing has to
be respected:
–tsuDAT >1/fCPU ~ 230,84ns
–thdDAT >1/fCPU ~ 230,84ns
In the ROM version of the ST7285, the I2C periph-
eral and FCPU are asynchronous, so no unexpect-
ed START or STOP condition can be detected.
Unexpected BTF flag setting after a STOP con-
dition
Due to the reason described in the previous para-
graph, the BTF flag can be set unexpectedly in the
I
2C interface of the ST72E85 after a STOP condi-
tion is detected in Slave mode.
To recover from this condition, reset and subse-
quently set the PE bit in the CR register when the
STOPF and BTF flags are set at the same time af-
ter a STOP condition detection.
The I
2C interface is not subject to this effect in the
ROM version of the ST7285.
Figure 31. I C Timing Diagram
SDA
SCL
tsuDAT
thdDAT
DATA bit
START bit


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