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ST7285C Datasheet(HTML) 57 Page - STMicroelectronics

Part No. ST7285C
Description  8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST7285C Datasheet(HTML) 57 Page - STMicroelectronics

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ST7285C
I
2C BUS INTERFACE (Cont’d)
4.5.5 Register Description
CLOCK CONTROL REGISTER (CCR)
Address: 002Bh
Read / Write
Reset Value: 00h
b7: FM/SM Fast / Standard I
2Cmode
When the bit is set to 1 the interface operates in
the fast I2C bus mode.
When the bit is set to 0 the interface operates in
the standard I
2C bus mode.
b6-0: D6-D0
7 bit divider programming
Implementation of a programmable clock divider
In Standard I2C mode:
Fscl = PHI1/(2x([D6..D0]+2)); in this case, Fscl
varies between 15.75KHz and 100 KHz (if
PHI1=4MHz).
In Fast I
2C mode:
Fscl = PHI1/(3x([D6..D0]+2)); in this case, Fscl
varies
between
10.5
KHz
and
333KHz
(if
PHI1=4MHz).
Table 8. Example of SCL frequency with PHI1 = 4 MHz in Standard I2C mode
70
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
FM/SM
D6
D5
D4
D3
D2
D1
D0
Fscl(Khz)
0
0
01
0010
100
0
0
01
1011
70
0
0
10
0110
50
0
1
00
1110
25
0
1
11
1111
15.75
1
0
00
0010
333
1
0
00
0101
190
1
0
00
0110
167
1
0
00
1101
89
1
0
01
1011
43
1
1
11
1111
10.5


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