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STA120 Datasheet(PDF) 8 Page - STMicroelectronics |
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STA120 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 15 page STA120 8/15 This timing is illustrated in Figure 5. The C output contains the channel status bits with CBL rising indicating the start of a new channel status block. CBL is high for the first four bytes of channel status (32 frames or 64 samples) and low for the last 20 bytes of channel status (160 frames or 320 samples). The U output contains the User Channel data. The V bit is OR'ed with the ERF flag and output on the VERF pin. This indicates that the audio sample may be in error and can be used by interpolation filters to interpolate through the error. ERF being high indicates a serious error occurred on the transmission line. There are three errors that cause ERF to go high: a parity error or biphase coding violation during that sample, or an out of lock PLL receiver. Timing for the above pins is illustrated in Figure 5. Multifunction Pins There are seven multifunction pins which contain either error and received frequency information, or chan- nel status information, selectable by SEL. Figure 3. Audio Serial Port Formats FSYNC(out) MSB LSB MSB LSB MSB LEFT RIGHT SCK(out) SDATA(out) FSYNC(in) MSB LSB MSB LSB MSB LEFT RIGHT SCK(in) SDATA(out) FSYNC(out) MSB LSB MSB LSB MSB LEFT RIGHT SCK(out) SDATA(out) FORMAT 0: FORMAT 1: FORMAT 2: FSYNC(out) MSB LSB MSB LSB MSB LEFT RIGHT SCK(out) SDATA(out) FSYNC(out) LSB MSB LSB SCK(out) SDATA(out) FORMAT 4: FORMAT 5: LEFT RIGHT LSB MSB 16 Bits 16 Bits FSYNC(out) LSB MSB LSB SCK(out) SDATA(out) FORMAT 6: LEFT RIGHT LSB MSB 18 Bits 18 Bits FSYNC(out) MSB LSB MSB SCK(out) SDATA(out) FORMAT 7: LEFT RIGHT MSB LSB D97AU610 M2 M1 M0 0 0 0 0 0 1 0 1 0 FSYNC(in) MSB LSB MSB LSB MSB LEFT RIGHT SCK(in) SDATA(out) FORMAT 3: 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 |
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