11

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

Row Active

The Bank Activation cimmand is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The

DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command

must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or

precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between inter-

Read Bank

This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating

CS, CAS, and deassertig WE, RAS at the same clock sampling(rising) edge as described in the command truth table. The length of

the burst and the CAS latency time will be determined by the values programmed during the MRS cycle.

Write Bank

This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating

RAS, CS, WE, and deassertig RAS at the same clock sampling(rising) edge as described in the command truth table. The length

of the burst will be determined by the values programmed during the MRS cycle.

Bank Activation Command Cycle

0

1

2

3

4

5

Tn

Tn+1

CK

CK

Address

Command

Bank A

Row Addr.

Bank A

Col. Addr.

NOP

NOP

NOP

Write A

Bank B

Bank A

Activate

with Auto

Bank B

Activate

Row Addr.

Bank A

Row Addr.

Bank A

Activate

NOP

: Don’t Care

Figure.4 Bank activation command cycle timing

Precharge