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A6282ELP-T Datasheet(PDF) 10 Page - Allegro MicroSystems |
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A6282ELP-T Datasheet(HTML) 10 Page - Allegro MicroSystems |
10 / 13 page 16-Channel Constant-Current LED Driver A6282 10 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Load Supply Voltage (VLED) This device is designed to operate with driver voltage drops (VDS) of 1.0 to 3.0V. If higher voltages are dropped across the driver, package power dissipation will increase. To minimize package power dissipation, it is recommended to use the lowest possible load supply voltage, VLED, or to set a series voltage drop, VDROP, according to the following formula: VDROP = VLED – VF – VDS , where VF is the LED forward voltage. For reference, typical LED forward voltages are: LED Type VF (V) White 3.5 to 4.0 Blue 3.0 to 5.5 Green 1.8 to 2.5 Yellow 2.0 to 2.5 Amber 1.9 to 3.0 Red 1.6 to 2.5 Infrared 1.2 to 1.8 UV 3.0 to 4.0 VDROP = IO×RDROP for a single driver, for a Zener diode (VZ), or for a series string of silicon diodes (approximately 0.7 V per diode) for a group of drivers (these configurations are shown in the figure below). If the available voltage source will cause unacceptable power dissipation and series resistors or diodes are undesirable, a voltage regulator can be used to provide VLED. Pattern Layout To save pins and board space, the A6282 uses one pin for both logic ground and power ground. Therefore, achieving optimal performance requires careful attention to layout. Following the suggestions below will improve the analog performance and logic noise immunity. 1. Place the REXT resistor as close as possible to the REXT pin and GND pin. This will minimize parasitic inductance and capacitance. 2. Use a separate line to the device GND pin for REXT, and sepa- rate lines for the decoupling capacitors. The lines should join at ground. This star grounding will improve output load regulation and minimize any chance of oscillation. The REXT ground line should carry only the small current from the internal voltage reference at REXT. The high AC currents flowing through the decoupling capacitors and their resistive and inductive PCB lines cause noise (ground bounce) on the capacitor ground lines. Such noise could disturb the reference voltage at REXT and promote oscillation. Connect the exposed thermal pad of the ES and LP packages to the power ground, along with the decoupling capacitors, and not to the ground line for REXT. 3. Keep the output drive lines (OUT0 through OUT15) away from the REXT pin to avoid coupling of the output signal into the reference for the current sources. Output lines should not run adjacent to the REXT pin or directly under the REXT pin. 4. Use decoupling capacitors on the VDD pin and the LED sup- ply bus. Place the logic decoupling capacitor (0.1 μF, one for each A6282) as close as possible to the VDD pin. Use at least one 10 μF capacitor from the LED supply line to device ground for at least every two A6282s. 5. Use multilayer boards if possible. Package Power Dissipation The maximum allowable package power dissipation based on package type is determined by: PD(max) = (150 – TA) / RJA, where RJA is the thermal resistance of the package, determined experimentally. Power dissipation levels based on the package are shown in the Thermal Characteristics table. The actual package power dissipation is determined by: PD(act) = DC ×(VDS ×IO×16) + (VDD×IDD), where DC is the duty cycle. The value 16 is the maximum number of available device outputs, representing the worst-case scenario (displaying all 16 LEDs). When the load supply voltage, VLED, is greater than 3 to 5 V, and PD(act) > PD(max), an external voltage reducer (VDROP) must be used (figure at left). Reducing DC will also reduce power dissipation. The ES and LP packages contain an exposed thermal pad on the bottom of the package for enhanced heat dissipation. Connect this pad to a large power ground plane using thermal vias. JEDEC documents JESD51-3 and JESD51-5 give suggestions for PCB and thermal via designs. V DS V F V DROP V LED V DS V F V DROP V LED V DS V F V DROP V LED Application Information Typical application voltage drops |
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