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V54C316162VC Datasheet(PDF) 4 Page - Mosel Vitelic, Corp |
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V54C316162VC Datasheet(HTML) 4 Page - Mosel Vitelic, Corp |
4 / 22 page 4 V54C316162VC Rev. 1.4 December 2001 MOSEL VITELIC V54C316162VC Signal Pin Description Pin Name Input Function CLK Clock Input System clock input. Active on the positive rising edge to sample all inptus CKE Clock Enable Activates the CLK signal when high and deactivates the CLK when low. CKE low initiates the power down mode, suspend mode, or the self refresh mode CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMi RAS Row Address Strobe Latches row addresses on the positive edge of CLK with RAS low. Enables row access & precharge CAS Column Address Strobe Latches column addresses on the positive edge of CLK with CAS low. Enables column access WE Write Enable Enables write operation A0-A10 Address During a bank activate command, A0-A10 defines the row address. During a read or write command, A0-A7 defines the column address. In addition to the column address A10 is used to invoke auto precharge BA define the bank to be precharged. A10 is low, auto precharge is disabled during a precharge cycle, If A10 is high, both bank will be precharged , if A10 is low, the BA is used to decide which bank to precharge. If A10 is high, all banks will be precharged. BA Bank Select Selects which bank to activate. BA low select bank A and high selects bank B I/O1-I/O16 Data Input/Output Data inputs/output are multiplexed on the same pins UDQM, LDQM Data Input/Output Mask Makes data output Hi-Z. Blocks data input when DQM is active VDD/VSS Power Supply/Ground Power Supply. +3.3V ± 0.3V/ground VDDQ/VSSQ Data Output Power/Ground Provides isolated power/ground to DQs for improved noise immunity NC No Connection |
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