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V54C316162VC-5 Datasheet(PDF) 1 Page - Mosel Vitelic, Corp |
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V54C316162VC-5 Datasheet(HTML) 1 Page - Mosel Vitelic, Corp |
1 / 22 page MOSEL VITELIC 1 V54C316162VC 200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 V54C316162VC Rev. 1.4 December 2001 V54C316162VC -5 -55 -6 -7 Unit Clock Frequency (tCK) 200 183 166 143 MHz Latency 3333 clocks CycleTime(tCK)5 5.5 6 7 ns Access Time (tAC) 5 5.3 5.5 5.5 ns Features s JEDEC Standard 3.3V Power Supply s The V54C316162VC is ideally suited for high performance graphics peripheral applications s Single Pulsed RAS Interface s Programmable CAS Latency: 2, 3 s All Inputs are sampled at the positive going edge of clock s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 1, 2, 4, 8 and Full Page for Sequential and 1, 2, 4, 8 for Interleave s UDQM & LDQM for byte masking s Auto & Self Refresh s 2K Refresh Cycles/32 ms s Burst Read with Single Write Operation Description The V54C316162VC is a 16,777,216 bits syn- chronous high data rate DRAM organized as 2 x 524,288 words by 16 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation. |
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