V54C3256 datasheet(11/52 Pages) MOSEL

Part #	V54C3256

Description	256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4

Download	52 Pages

Scroll/Zoom	100%

Manufacturer	MOSEL [Mosel Vitelic, Corp]

Direct Link	http://www.moselvitelic.com

Logo

11 / 52 page

11

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Signal Pin Description

Type

Signal

Polarity

Function

CLK

Input

Pulse

Positive

Edge

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the

clock.

CKE

Input

Level

Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby

initiates either the Power Down mode or the Self Refresh mode.

CS

Input

Pulse

Active Low CS enables the command decoder when low and disables the command decoder when

high. When the command decoder is disabled, new commands are ignored but previous

operations continue.

RAS, CAS

WE

Input

Pulse

Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the

command to be executed by the SDRAM.

A0 - A11

Input

Level

—

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)

when sampled at the rising clock edge.CAn depends from the SDRAM organization:

• 64M x 4 SDRAM CA0–CA9, CA11.

• 32M x 8 SDRAM CA0–CA9.

• 16M x 16 SDRAM CA0–CA8.

In addition to the column address, A10(=AP) is used to invoke autoprecharge operation

at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and

BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.

During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1

to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are

used to define which bank to precharge.

BA0,

BA1

Input

Level

—

Selects which bank is to be active.

DQx

Input

Output

Level

—

Data Input/Output pins operate in the same manner as on conventional DRAMs.

LDQM

UDQM

Input

Pulse

Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-

pled high. In Read mode, DQM has a latency of two clock cycles and controls the output

buffers like an output enable. In Write mode, DQM has a latency of zero and operates as

a word mask by allowing input data to be written if it is low but blocks the write operation

if DQM is high.

VCC, VSS

Supply

Power and ground for the input buffers and the core logic.

VCCQ

VSSQ

Supply

—

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

Similar Part No. - V54C3256

Manufacturer	Part #	Datasheet	Description
Mosel Vitelic, Corp	V54C3256164VAB	838Kb / 52P	256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
	V54C3256164VALT6	838Kb / 52P	256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
	V54C3256164VAT	838Kb / 52P	256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
	V54C3256164VBS	838Kb / 52P	256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
	V54C3256164VBT	838Kb / 52P	256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4

More results

Similar Description - V54C3256

Manufacturer	Part #	Datasheet	Description
Mosel Vitelic, Corp	V54C3256164VALT6	838Kb / 52P	256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
Mosel Vitelic, Corp	V54C3256164VBUC	651Kb / 45P	LOW POWER 256Mbit SDRAM 3.3 VOLT, 54-BALL SOC BGA 54-PIN TSOPII 16M X 16
List of Unclassifed Man...	V55C2256164VB	560Kb / 46P	256Mbit MOBILE SDRAM 2.5 VOLT FBGA PACKAGE 16M X 16
Mosel Vitelic, Corp	V55C2128164V	591Kb / 44P	128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16
Integrated Silicon Solu...	IS42S86400B	913Kb / 61P	64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM
Samsung semiconductor	K4S560432B	130Kb / 11P	256Mbit SDRAM 16M x 4bit x 4 Banks Synchronous DRAM LVTTL
Samsung semiconductor	K4S560432A	127Kb / 10P	256Mbit SDRAM 16M x 4bit x 4 Banks Synchronous DRAM LVTTL
Mosel Vitelic, Corp	V436516R04VATG-10PC	223Kb / 12P	3.3 VOLT 16M x 64 using 8M x 16 PC100 UNBUFFERED SDRAM MODULE
Mosel Vitelic, Corp	V436516R04VATG-75	189Kb / 12P	3.3 VOLT 16M x 64 using 8M x 16 PC133 UNBUFFERED SDRAM MODULE
Siemens Semiconductor G...	HYS6472V16200GU	84Kb / 17P	3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules

More results

V54C3256 Datasheet(PDF) 11 Page - Mosel Vitelic, Corp

V54C3256 Datasheet(HTML) 11 Page - Mosel Vitelic, Corp

Similar Part No. - V54C3256

Similar Description - V54C3256

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL