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56800E Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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56800E Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 60 page  56F827 Technical Data, Rev. 12 4 Freescale Semiconductor Part 1 Overview 1.1 56F827 Features 1.1.1 Processing Core • Efficient 16-bit 56800 family processor engine with dual Harvard architecture • As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • Two 36-bit accumulators including extension bits • 16-bit bidirectional shifter • Parallel instruction set with unique processor addressing modes • Hardware DO and REP loops • Three internal address buses and one external address bus • Four internal data buses and one external data bus • Instruction set supports both DSP and controller functions • Controller style addressing modes and instructions for compact code • Efficient C Compiler and local variable support • Software subroutine and interrupt stack with depth limited only by memory • JTAG/OnCE Debug Programming Interface 1.1.2 Memory • Harvard architecture permits as many as three simultaneous accesses to Program and Data memory • On-chip memory including a low-cost, high-volume Flash solution — 64K words of Program Flash —1K words of Program RAM — 4K words of Data RAM — 4K words of Data Flash • Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states — As much as 64 K × 16 Data memory — As much as 64 K × 16 Program memory 1.1.3 Peripheral Circuits for 56F827 • One 10 channel, 12-bit, Analog-to-Digital Converter (ADC) • One General Purpose Quad Timer totaling 4 pins • One Serial Peripheral Interface with configurable four-pin port multiplexed with two Serial Communications Interfaces totalling 4 pins or 4 GPIO pins • Three Serial Communication Interfaces with 2 pins each (or 6 additional GPIO pins) • Two Serial Peripheral Interface with configurable four-pin port (or 4 additional GPIO pins) |
Similar Part No. - 56800E |
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Similar Description - 56800E |
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