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TP23753 Datasheet(PDF) 2 Page - Texas Instruments |
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TP23753 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 27 page ABSOLUTE MAXIMUM RATINGS (1) DISSIPATION RATINGS TPS23753 SLVS853A – JUNE 2008 – REVISED JUNE 2008.............................................................................................................................................................. www.ti.com This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. PRODUCT INFORMATION(1) DEVICE DUTY CYCLE POE UVLO ON / HYST. PACKAGE MARKING TPS23753 0 – 80% 35/4.5 PW (TSSOP-14) TP23753 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Voltags are with respect to VSS (unless otherwise noted) VALUE UNIT VDD, VDD1, DEN, RTN (2) –0.3 to 100 V VDD1 to RTN –0.3 to 100 V CLS(3) –0.3 to 6.5 V VI Input voltage range [APD, BLNK(3), CTL, FRS(3), VB (3)] to RTN –0.3 to 6.5 V CS to RTN –0.3 to VB V VC to RTN –0.3 to 19 V GATE to RTN –0.3 to VC + 0.3 V Sourcing current VB Internally limited mA Average sourcing or sinking current GATE 25 mARMS HBM 2 kV ESD rating CDM 500 V ESD – system level (contact/air)(4) 8/15 kV –40 to Internally TJ Operating junction temperature range °C Limited (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) IRTN = 0 for VRTN > 80V. (3) Do not apply voltage to these pins. (4) Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the TPS23753EVM-001 (HPA304-001) evaluation module (documentation available on the web). These were the test levels, not the failure threshold. θ JT θ JA θ JA PACKAGE (°C/W)(1) (°C/W)(2) (°C/W)(1) PW (TSSOP-14) 0.97 173.6 99.3 (1) JEDEC method with high-k board (4 layers, 2 signal and 2 planes). (2) JEDEC method with low-k board (2 signal layers). 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753 |
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